SLVUC73B January   2022  – February 2024 TPS7H4003-SEP

 

  1.   1
  2.   TPS7H4003EVM Evaluation Module (EVM)
  3.   Trademarks
  4. 1TPS7H4003EVM Overview
    1. 1.1 Features
    2. 1.2 Applications
  5. 2TPS7H4003EVM Default Configuration
  6. 3TPS7H4003EVM Initial Setup
  7. 4TPS7H4003EVM Testing
    1. 4.1 Output Voltage Regulation
    2. 4.2 Output Voltage Ripple
    3. 4.3 Soft Startup
    4. 4.4 Transient Response to Positive and Negative Load Step (9A to 18A to 9A)
    5. 4.5 Loop Frequency Response
    6. 4.6 Setup
  8. 5TPS7H4003EVM Schematic
  9. 6TPS7H4003EVM Bill of Materials (BOM)
  10. 7Board Layout
  11. 8Support Resources
  12. 9Revision History

Board Layout

The following is the layer stack of the TPS7H4003EVM board.

GUID-20220114-SS0I-1TW7-VQTD-NZFFGVWC9ZJ7-low.pngFigure 7-1 Top Overlay
GUID-20220114-SS0I-FQSF-8TRJ-0TNLSZHJR0D7-low.pngFigure 7-2 Top Solder
GUID-20220114-SS0I-MT4B-J46X-67GVWGH8NN5Z-low.pngFigure 7-3 Top Layer
GUID-20220114-SS0I-ZGWK-NDTK-BF47CWXL8K80-low.pngFigure 7-4 Signal Layer One
GUID-20220114-SS0I-DHT7-6NGC-4WJRXPVVRGX6-low.pngFigure 7-5 Signal Layer Two
GUID-20220114-SS0I-LNRW-SRHB-PV870PDRNVKH-low.pngFigure 7-6 Signal Layer Three
GUID-20220114-SS0I-MXGV-H7Q1-DQDZL46CB94Z-low.pngFigure 7-7 Signal Layer Four
GUID-20220114-SS0I-PR9F-HGM1-ZLG9CCBDT416-low.pngFigure 7-8 Signal Layer Five
GUID-20220114-SS0I-JKK5-PHST-0B6DQ3CBNBTT-low.pngFigure 7-9 Signal Layer Six
GUID-20220114-SS0I-VS2M-Z1TK-GWMG6WQLZCWT-low.pngFigure 7-10 Bottom Layer
GUID-20220114-SS0I-Z8RH-DQF5-NLPVHB2SMN6F-low.pngFigure 7-11 Bottom Solder
GUID-20220114-SS0I-JZGF-G8QV-NFW0RBQTTHST-low.pngFigure 7-12 Bottom Overlay
GUID-20220114-SS0I-7HNV-Q8F6-DP9XKWWJCXBW-low.png Figure 7-13 Drill Drawing
GUID-20220114-SS0I-FR0Z-5BWG-STK6JGT3QG34-low.png Figure 7-14 PCB Dimensions