SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

A Non-NVM Registers

The PMIC register map contains NVM and non-NVM bits. Register addresses 0x00 to 0x27 contains the NVM bits which are backed up by EEPROM. This register settings can be changed by I2C and default values can be re-programmed as described in the programming guide. The reset value for each of the NVM bits is marked as "X" in the data sheet register map as those can be re-programmed and are unique for each orderable part number.

Non-NVM bits are located in register addresses 0x28 to 0x41. These registers settings can be changed by I2C but the default values cannot be re-program. Register settings for non-NVM bits go back to their default values after a power cycle and every time the PMIC enters Initialize state. The default value for non-NVM bits can be found in the data sheet register map, under "Reset" column.