SLVUCM5 july   2023 TPS65219 , TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

C PMIC Configurable Fields

This section shows the list of programmable NVM fields for each of the PMIC power and digital resources. Some of the register fields have "x" to simplify the list. Replace "x" with the corresponding rail number to identify the correct register field in the data sheet or programming guide. Similarly, for the sequence slot duration, "y" was used to simplify the list but those can be replaced with the specific slot#.

GUID-20230710-SS0I-W7WX-GDBV-9ZXV643CJSZF-low.svg Figure C-1 NVM programmable Fields