SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.3 Regulator Voltage Settings

This section describes how each of the PMIC power resources are configured.

Table 3-4 Buck Regulator Settings
PMIC RailRegister AddressField NameValueDescription
BUCK10x0ABUCK1_VSET

(Output Voltage)

0x60.750V
0x0ABUCK1_UV_THR_SEL

(UV threshold)

0x0-5% UV detection
0x0ABUCK1_BW_SEL

(Bandwidth)

0x1high bandwidth
0x1D BUCK1_DVS_STBY 0x0 No DVS transition in STBY
0x1D BUCK1_VSET_STBY 0x00 0ms
BUCK20x09 BUCK2_VSET

(Output Voltage)

0x241.800V
0x09 BUCK2_UV_THR_SEL

(UV threshold)

0x0-5% UV detection
0x09 BUCK2_BW_SEL

(Bandwidth)

0x0low bandwidth
0x1C BUCK2_DVS_STBY 0x0 No DVS transition in STBY
0x1C BUCK2_VSET_STBY 0x00 0ms
BUCK30x08BUCK3_VSET

(Output Voltage)

0x141.100V
0x08BUCK3_UV_THR_SEL

(UV threshold)

0x0-5% UV detection
0x08BUCK3_BW_SEL

(Bandwidth)

0x0low bandwidth
0x19 BUCK3_DVS_STBY 0x0 No DVS transition in STBY
0x19 BUCK3_VSET_STBY 0x00 0ms
Table 3-5 LDO Regulator Settings
PMIC Rail Register Address Field Name Value Description
LDO1 0x05 LDO1_VSET 0x1A 1.800V
0x05 LDO1_LSW_CONFIG 0x0 LDO Mode
0x1E LDO1_UV_THR 0x0 -5% UV detection
0x04 LDO1_DVS_STBY 0x0 No DVS transition in STBY
0x04 LDO1_VSET_STBY 0x1A 1.800V
LDO2 0x06 LDO2_VSET 0x05 0.750V
0x06 LDO2_LSW_CONFIG 0x0 LDO Mode
0x1E LDO2_UV_THR 0x0 -5% UV detection
0x07 LDO2_DVS_STBY 0x0 No DVS transition in STBY
0x07 LDO2_VSET_STBY 0x05 0.750V
Note:
  • If a LDO is configured in LSW-mode, UV-detection is not supported.
  • If LDO is configured as load-switch (LSW_mode), the desired voltage does not need to be configured in the LDOx_VOUT register.
  • In LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the FET-resistance.