SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.9 Discharge Check

Each rail is discharged prior to its enable in the power sequence or by I2C. This discharge check can be skipped by setting bit BYPASS_RV_FOR_RAIL_ENABLE.

Active discharge is enabled by default and is not NVM based. If desired, this setting can be disabled after each VSYS-power-cycle. In case active discharge on a rail is disabled, it does not gate the disable of the subsequent rail, but the sequence is purely timing based. In case of residual voltage, the RV-bit is set regardless. During RESET or OFF-request, the discharge configuration is not reset, as long as VSYS is present.

Table 3-15 Discharge Check
Register AddressField NameValueDescription
0x1EBYPASS_RV_FOR_RAIL_ENABLE0x0Discharged checks enforced