SLVUD64 February   2025 TPS2HC120-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Connection Descriptions
      1. 2.1.1 Connections and Test Points
      2. 2.1.2 Jumper Configurations
  8. 3Implementation Results
    1. 3.1 Variable Resistor for CS and CL
      1. 3.1.1 Current Sense Resistor
      2. 3.1.2 Adjustable Current Limit
  9. 4Hardware Design Files
    1. 4.1 TPS2HC120EVM Schematic
    2. 4.2 TPS2HC120EVM Assembly Drawings and Layout
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks

4.2 TPS2HC120EVM Assembly Drawings and Layout

The design of the TPS2HC120-Q1 printed-circuit board (PCB) is shown in Figure 4-2 to Figure 4-5. The EVM is designed using FR4 material, four-layer (2s2p), 2 × 70µm cubic inch top and bottom layers, and 2 × 35µm cubic inch internal plane layers. All components are in an active area on the top side and all active traces to the top and bottom layers to allow the user to easily view, probe, and evaluate. Moving components to both sides of the PCB offers additional size reduction for space-constrained systems.

TPS2HC120EVM TPS2HC120EVM First Layer (Top View) Figure 4-2 TPS2HC120EVM First Layer (Top View)
TPS2HC120EVM TPS2HC120EVM Second Layer GND (Top View) Figure 4-3 TPS2HC120EVM Second Layer GND (Top View)
TPS2HC120EVM TPS2HC120EVM Third Layer VCC (Top View) Figure 4-4 TPS2HC120EVM Third Layer VCC (Top View)
TPS2HC120EVM TPS2HC120EVM Fourth Layer (Top View) Figure 4-5 TPS2HC120EVM Fourth Layer (Top View)