SLVUD64 February   2025 TPS2HC120-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Connection Descriptions
      1. 2.1.1 Connections and Test Points
      2. 2.1.2 Jumper Configurations
  8. 3Implementation Results
    1. 3.1 Variable Resistor for CS and CL
      1. 3.1.1 Current Sense Resistor
      2. 3.1.2 Adjustable Current Limit
  9. 4Hardware Design Files
    1. 4.1 TPS2HC120EVM Schematic
    2. 4.2 TPS2HC120EVM Assembly Drawings and Layout
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks

2.1.1 Connections and Test Points

Connector and Test PointDescription

J4, TP6

Supply voltage VS

J24, TP15

Output voltage OUT1

J27, TP18

Output voltage OUT2

J5, TP13, TP14, and TP19–TP22

System GND

TP12

GND_IC test point

TP1, TP3

ENABLE test points EN1 and EN2

TP4, TP5

SELx test points SEL0 and SEL1

TP11

DIAG_EN test point

TP7

FLT test point

TP8

LPM test point

TP9

SNS test point

J14 (GPIO connection)

1 connects to FLT pin, 2 connects to LPM pin, and 3 connects to SNS pin.