SLVUDG2 October   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 Jumper Information
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Additional Information
    1. 4.1 Trademarks

2.3 Header Information

J1 and J6: analog inputs IN_P and IN_N

J2 and J5: latch enable inputs LE_P and LE_N

J3 and J4: CML outputs OUT_P and OUT_N

TP1: VCCI

TP2: VEE

TP3: VCCO

TP4, TP5, TP6: System Ground

TP9: Hysteresis control pin