SLVUDI9 October   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Headers and Test Points Information
    2. 2.2 Connector Information
    3. 2.3 Indicator LEDs
    4. 2.4 Hardware Setup
  9. 3Software
    1. 3.1 Web GUI Access or Local GUI Installation
    2. 3.2 Connecting EVM to GUI
    3. 3.3 GUI Overview
    4. 3.4 DRV81545 GUI
    5. 3.5 DRV81646 GUI
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Trademarks

3.5 DRV81646 GUI

The DRV81646 GUI is utilized in both the DRV81646EVM and DRV81646DGQEVM. The accompanying GUI software supports interaction with the device via both Hardware and SPI interface. The DRV81646 GUI features two primary pages: the Hardware intrface page and the SPI interface page. The Hardware interface page enables control of the device through input PWM, allowing for intuitive management of device settings. The nFAULT LED serves as a visual indicator, signaling that either over-current or over-temperature protection has been triggered for one or more channels. In contrast, the SPI interface page offers ON/OFF control through the transmission of SPI commands, as well as detailed fault information for each channel, providing a more general understanding of device performance and allowing for targeted troubleshooting.

Figure 3-7 below shows the Load Control Panel under the Hardware mode with the main sections enclosed in red boxes with a letter assigned.

DRV81646EVM, DRV81646DGQEVM, DRV81545EVM, DRV81X4XEVM DRV81646EVM Driver Control Panel Hardware InterfaceFigure 3-7 DRV81646EVM Driver Control Panel Hardware Interface
Table 3-2 DRV81646 GUI Hardware Interface Overview

Component label

Description

A

Driver Configuration

Interface Selection: The device offers two interface options: Hardware and SPI.

  • Hardware Interface: Under this configuration, channels are controlled using PWM input. The interface is selected by connecting an appropriate resistor to the RSLEW/CNT pin through the MCU.

  • SPI Interface: The SPI controls the outputs through SPI commands, which are executed by setting the control register bits.

To switch between the Hardware and SPIs, it is essential to power down the device, change the interface, and then power it up.

  • Rise/Fall Time: This setting configures the output slew rate by connecting an appropriate resistor to the RSLEW/CNT pin. Note that power cycling is required to apply changes to the slew rate

B

Block Diagram of DRV81646.

C

OUT1 Channel control parameters.

  • IN1 Duty Cycle: The IN1 PWM duty cycle is adjustable from 0% to 100%.

  • IN1 Frequency: The IN1 PWM frequency can be varied between 0Hz and 250kHz, with selectable units (Hz or kHz).

  • IN1 Ramp Rate: Controls the rate of duty cycle increment.

  • OUT1 Enable/Disable: This toggle switch governs the application of the IN1 PWM signal.

    • Enabled: The IN1 PWM signal is applied to the IN1 pin.

    • Disabled: The IN1 PWM signal is not applied to the IN1 pin.

  • Current: Displays the output current measured at the SRC pin of each channel, providing a real-time indication of the current flow.

D

  • Device: Device name

  • Firmware Version: EVM firmware version

  • VM voltage: supply voltage value.

E

  • nFAULT Pin Status:

    • Green: Indicates normal operation with no active fault conditions.

    • Red: : Indicates that either overcurrent or overtemperature protection has been activated for one or more channels.

Figure 3-7 below shows the Load Control Panel under the SPI mode with the main sections enclosed in red boxes with a letter assigned.

DRV81646EVM, DRV81646DGQEVM, DRV81545EVM, DRV81X4XEVM DRV81646EVM Driver Control Panel SPIFigure 3-8 DRV81646EVM Driver Control Panel SPI
Table 3-3 DRV81646 GUI SPI Interface Overview
Component labelDescription
A

Driver Configuration

Interface Selection: The device offers two interface options: Hardware and SPI.

  • Hardware Interface: Under this configuration, channels are controlled using PWM input. The interface is selected by connecting an appropriate resistor to the RSLEW/CNT pin through the MCU.
  • SPI: The SPI controls the outputs through SPI commands, which are executed by setting the control register bits.
To switch between the Hardware and SPIs, it is essential to power down the device, change the interface, and then power it back up.

  • Rise/Fall Time: This setting configures the output slew rate by connecting an appropriate resistor to the RSLEW/CNT pin. Note that power cycling is required to apply changes to the slew rate

BBlock Diagram of DRV81646.
C

OUT1 Channel control parameters.

  • IN1 Duty Cycle: The IN1 PWM duty cycle is adjustable from 0% to 100%.
  • IN1 Frequency: The IN1 PWM frequency can be varied between 0Hz and 250kHz, with selectable units (Hz or kHz).
  • IN1 Ramp Rate: Controls the rate of duty cycle increment.
  • OUT1 Enable/Disable: This toggle switch governs the application of the IN1 PWM signal.
    • Enabled: The IN1 PWM signal is applied to the IN1 pin.
    • Disabled: The IN1 PWM signal is not applied to the IN1 pin.
  • Current: Displays the output current measured at the SRC pin of each channel, providing a real-time indication of the current flow.
D
  • Device: Device name
  • Firmware Version: EVM firmware version
  • VM voltage: supply voltage value.
E
  • Fault_CHx:
    • Green: Indicates is working normally since last SPI transaction.
    • Red: Fault occurred on channel X. This bit is set if channel X encountered a fault since the last SPI transaction. The bit clears when nSCS is pulled back high at the end of valid SPI transaction (parity checks pass)
  • SPI_ERROR:
    • Green: Indicates SCLK number is correct and parity check is passed.
    • Red: Indicates that the parity checks on received data bits does not match with received parity bits or the number of SCLK pulses received when NSCS is low is not a multiple of 8.

F

SPI Response Packet:

The current channel states of individual channels are latched on the falling edge of the nSCS pin (when SPI transaction is initiated). Latched faults are cleared on rising edge of the nSCS pin.

  • FAULT_CHx :

    • 0: Channel is working normally since last SPI transaction.

    • 1: Fault occurred on channel X. This bit is set if channel X encountered a fault since the last SPI transaction. The bit clears when NSCS is pulled back high at the end of valid SPI transaction ( parity checks pass)

  • SPISTAT: is defined as SPISTAT = (SDI) & NOT(SPI_ERROR).

A SPI error on current transaction is reported in the next transaction by the driver pulling SDO low/high during the tH_SCLK interval. The SDO state is set to SPISTAT = (SDI) & NOT(SPI_ERROR). The easiest way to read the SPISTAT value is to hold SDI=1 during the tH_SCLK interval and read SPISTAT after tSDOHIZ, so that if there is a SPI error then SPISTAT=0, else SPISTAT=1.

G

SPI Input Packet:

  • CHx_N_Stat: When CHx_N_State bit is set to 1, internal logic switches on the corresponding low side output channel N-FET. Setting CHx_N_State to 0 switches off the corresponding OUTx. The bits are linked to CHx toggle switches.

  • R/W : The R/W (Read/Write) bit determines if the CHx_N_state bit is propagated to outputs or not. Set R/W to 1 to perform write operation. Set R/W to 0 to read the existing channel state and fault information while leaving current output state unchanged. A fault on an output switches off the output and the state returns 0.

  • Parity bits P[2:0]: P[2:0] is a set of 3 parity bits which are used to check the correctness of received data word. If the parity check fails then the output states are not updated. The parity bits are calculated as follows, where ⊕ is XOR:

    • P[2] : B7 ⊕ B6 ⊕ B5

    • P[1] : B6 ⊕ B5 ⊕ B4

    • P[0] : B5 ⊕ B4 ⊕ B3

  • SDI: This bit is used for SPI error detection. See the data sheet for detail.