SLVUDM5 January   2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Input and Output Connections
  8. 3Implementation Results
    1. 3.1 Test Setup
      1. 3.1.1 Start-Up Procedure
    2. 3.2 Output Current Setting
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6References

4.2 Layout

Figure 4-2 to Figure 4-4 show the board layout for the TPS923612EVM. The top layer contains the main power traces for PVIN, VOUT, and ground. Connections for the pins of the TPS923612 and a large area filled with ground are also on the top layer. Most of the signal traces are also located on the top side. The decoupling capacitors C4, and C5 are located as close to the IC as possible. Both the top layer and bottom layer use 2oz copper thickness.

TPS923612EVM TPS923612EVM Top AssemblyFigure 4-2 TPS923612EVM Top Assembly
TPS923612EVM TPS923612EVM Top LayerFigure 4-3 TPS923612EVM Top Layer
TPS923612EVM TPS923612EVM Middle Layer 1Figure 4-4 TPS923612EVM Middle Layer 1
TPS923612EVM TPS923612EVM Middle Layer 2Figure 4-5 TPS923612EVM Middle Layer 2
TPS923612EVM TPS923612EVM Bottom LayerFigure 4-6 TPS923612EVM Bottom Layer