SLVUDU6 April   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Interfaces
      1. 2.1.1 Analog Input
      2. 2.1.2 EVM Output Configurations and Descriptions
      3. 2.1.3 Amplifier Output
        1. 2.1.3.1 Differential Output (Diff.)
        2. 2.1.3.2 Fixed Gain Single-Ended Output With Internal Reference (SE Int)
        3. 2.1.3.3 Fixed Gain Ratiometric Output With VDD Reference (R Int)
        4. 2.1.3.4 Single-ended and Ratiometric Output With External Reference (SE/R Ext)
      4. 2.1.4 Modulator Output
        1. 2.1.4.1 Internal Clock Modulator (Mod. Int.)
        2. 2.1.4.2 External Clock Modulator (Mod. Ext.)
    2. 2.2 VDD Power Supply
    3. 2.3 EVM Operation
      1. 2.3.1 Analog Input
      2. 2.3.2 Outputs and VDD Power
      3. 2.3.3 Test Procedure
        1. 2.3.3.1 Equipment Setup
        2. 2.3.3.2 Procedure
  9. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2.1.3.1 Differential Output (Diff.)

The passive components of R9, R10, and C9 are populated as a low-pass differential filter to attenuate high frequency noise components. C11 and C12 can be populated to help with the filtering of any common-mode noise.

VDD and GND are accessible through the J2 terminal block. C7, C8 and C10 serve as decoupling capacitors for VDD and help keep the supply stable.

Using an oscilloscope, the user can observe the differential output signal on J3.3 (OUTP) and J3.2 (OUTN) with respect to J2.3 (GND).