SLWS214C October   2008  – May 2026 ADS61B29 , ADS61B49

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Configuration and Functions (LVDS Mode) — ADS61B49 and ADS61B29
    2. 4.2 Pin Configuration and Functions (CMOS Mode) – ADS61B49 and ADS61B29
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Electrical Characteristics – ADS61B49 and ADS61B29
    4. 5.4  Electrical Characteristics – ADS61B49 and ADS61B29
    5. 5.5  Electrical Characteristics – ADS61B49 and ADS61B29
    6. 5.6  Digital Characteristics – ADS61B49 and ADS61B29
    7. 5.7  Timing Requirements – LVDS and CMOS Modes
    8. 5.8  Typical Characteristics - ADS61B49
    9. 5.9  Typical Characteristics - ADS61B29
    10. 5.10 Typical Characteristics - Common Plots (both ADS61B49/61B29)
    11. 5.11 Contour Plots - ADS61B49/ADS61B29
    12. 5.12 Contour Plots - ADS61B49
    13. 5.13 Contour Plots - ADS61B29
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagrams
      1. 6.1.1 ADS61B29 Block Diagram
      2. 6.1.2 ADS61B49 Block Diagram
    2. 6.2 Feature Description
      1. 6.2.1 Device Configuration
      2. 6.2.2 Parallel Configuration Only
      3. 6.2.3 Serial Interface Configuration Only
      4. 6.2.4 Configuration Using Both The Serial Interface and Parallel Controls
      5. 6.2.5 Description of Parallel Pins
      6. 6.2.6 Serial Interface
        1. 6.2.6.1 Register Initialization
      7. 6.2.7 Serial Interface Timing Characteristics
      8. 6.2.8 Serial Register Readout
      9. 6.2.9 Reset Timing
    3. 6.3 Serial Register Map
      1. 6.3.1 Description of Serial Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Theory of Operation
      2. 7.1.2  Analog Input
        1. 7.1.2.1 Drive Circuit Requirements
        2. 7.1.2.2 Driving Circuit
        3. 7.1.2.3 Input Common-Mode
      3. 7.1.3  Reference
      4. 7.1.4  Clock Input
      5. 7.1.5  Fine Gain Control
      6. 7.1.6  Offset Correction
      7. 7.1.7  Power Down
        1. 7.1.7.1 Power-Down Global
        2. 7.1.7.2 Standby
        3. 7.1.7.3 Output Buffer Disable
        4. 7.1.7.4 Input Clock Stop
      8. 7.1.8  Power Supply Sequence
      9. 7.1.9  Digital Output Information
        1. 7.1.9.1 Output Interface
        2. 7.1.9.2 DDR LVDS Outputs
        3. 7.1.9.3 LVDS Buffer
        4. 7.1.9.4 Parallel CMOS Interface
        5. 7.1.9.5 Output Buffer Strength Programmability
        6. 7.1.9.6 CMOS Interface Power Dissipation
        7. 7.1.9.7 Output Data Format
      10. 7.1.10 Board Design Considerations
        1. 7.1.10.1 Grounding
        2. 7.1.10.2 Supply Decoupling
        3. 7.1.10.3 Exposed Pad
      11. 7.1.11 Definition of Specifications
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3 Serial Register Map

Table 6-7 Summary of Functions Supported by Serial Interface
REGISTER ADDRESSREGISTER FUNCTIONS(1)
A7–A0 IN HEXD7D6D5D4D3D2D1D0
00<RESET>
Software Reset		000000<SERIAL READOUT>
2000000<ENABLE LOW SPEED MODE>00
3F0<REF> (RESERVED)00<PDN GLOBAL><STANDBY><PDN OBUF>
41<LVDS CMOS>
Output interface		000000
44<CLKOUT POSN>
Output clock position control		00
5000000<DATA FORMAT>
2s complement or offset binary		0
51<CUSTOM PATTERN LOW>
5200<CUSTOM PATTERN HIGH>
530<ENABLE OFFSET CORR>000000
55<FINE GAIN ><OFFSET CORR TIME CONSTANT>
Offset correction time constant
6200000<TEST PATTERNS>
6300<PROGRAM OFFSET PEDESTAL >
(1) Multiple functions in a register can be programmed in a single write operation.