Product details

Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 790 Architecture Pipeline SNR (dB) 72.3 ENOB (Bits) 11.3 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 790 Architecture Pipeline SNR (dB) 72.3 ENOB (Bits) 11.3 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • Integrated High Impedance Analog Input Buffer
  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution — ADS61B49
  • 12-Bit Resolution — ADS61B29
  • 790 mW Total Power Dissipation at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
  • DC Offset Correction
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • 48-QFN Package (7mm × 7mm)
  • Pin Compatible with ADS6149 Family
  • APPLICATIONS
    • Multicarrier, Wide Bandwidth Communications
    • Wireless Multi-Carrier Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization Feedback ADC
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

  • Integrated High Impedance Analog Input Buffer
  • Maximum Sample Rate: 250 MSPS
  • 14-Bit Resolution — ADS61B49
  • 12-Bit Resolution — ADS61B29
  • 790 mW Total Power Dissipation at 250 MSPS
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
  • DC Offset Correction
  • Supports Input Clock Amplitude Down to 400 mVPP Differential
  • 48-QFN Package (7mm × 7mm)
  • Pin Compatible with ADS6149 Family
  • APPLICATIONS
    • Multicarrier, Wide Bandwidth Communications
    • Wireless Multi-Carrier Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization Feedback ADC
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).

The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.

The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 14-/12-Bit, 250-MSPS ADCs with Integrated Analog Input Buffer datasheet (Rev. B) 13 May 2009
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
User guide GC5325 System Evaluation Kit (Rev. F) 20 Apr 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

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Support software

HSADC-SPI-UTILITY ADS5400 EVM GUI

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Supported products & hardware

Support software

SBAC120 TIGAR Support Files

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Supported products & hardware

Simulation model

ADS61xx, ADS62Pxx HS IBIS Model (Rev. B)

SLWC088B.ZIP (653 KB) - IBIS Model
Calculation tool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware

Calculation tool

JITTER-SNR-CALC Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

Supported products & hardware

Supported products & hardware

Design tool

SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Supported products & hardware

Supported products & hardware

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins CAD symbols, footprints & 3D models
VQFN (RGZ) 48 Ultra Librarian

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