The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.
The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).
| Part number | Order | Sample rate (Max) (MSPS) | Features | Resolution (Bits) | Number of input channels | SNR (dB) | ENOB (Bits) | SFDR (dB) | Power consumption (Typ) (mW) | Input range (Vp-p) | Interface | Operating temperature range (C) | Analog input BW (MHz) | Input buffer | Package Group | Package size: mm2:W x L (PKG) | Rating | Architecture |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADS61B29 |
|
250 | High Performance | 12 | 1 | 70 | 11.28 | 86 | 790 | 2 |
DDR LVDS
Parallel CMOS |
-40 to 85 | 700 | Yes | VQFN | 48 | 48VQFN: 49 mm2: 7 x 7 (VQFN | 48) | Catalog | Pipeline |
| ADS61B23 |
|
80 | Low Power | 12 | 1 | 70 | 11.3 | 82 | 351 | 2 |
DDR LVDS
Parallel CMOS |
-40 to 85 | 450 | Yes | VQFN | 32 | 32VQFN: 25 mm2: 5 x 5 (VQFN | 32) | Catalog | Pipeline |
| ADS61B49 |
|
250 | High Performance | 14 | 1 | 72.4 | 11.63 | 86 | 790 | 2 |
DDR LVDS
Parallel CMOS |
-40 to 85 | 700 | Yes | VQFN | 48 | 48VQFN: 49 mm2: 7 x 7 (VQFN | 48) | Catalog | Pipeline |
