12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)
Product details
Parameters
Package | Pins | Size
Features
- Integrated High Impedance Analog Input Buffer
- Maximum Sample Rate: 250 MSPS
- 14-Bit Resolution — ADS61B49
- 12-Bit Resolution — ADS61B29
- 790 mW Total Power Dissipation at 250 MSPS
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off and 1-Vpp Full-Scale Operation
- DC Offset Correction
- Supports Input Clock Amplitude Down to 400 mVPP Differential
- 48-QFN Package (7mm × 7mm)
- Pin Compatible with ADS6149 Family
- APPLICATIONS
- Multicarrier, Wide Bandwidth Communications
- Wireless Multi-Carrier Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization Feedback ADC
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
Description
The ADS61B49 (ADS61B29) is a 14-bit (12-bit) A/D converter with a sampling rate up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48-QFN package. An integrated analog buffer makes it well-suited for multi-carrier, wide bandwidth communications applications. The buffer maintains constant performance and input impedance across a wide frequency range.
The ADS61B49 (ADS61B29) has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both Double Data Rate (DDR) LVDS and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (-40°C to 85°C).
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | 14-/12-Bit, 250-MSPS ADCs with Integrated Analog Input Buffer datasheet (Rev. B) | May 13, 2009 |
| Application notes | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | May 22, 2015 | |
| Application notes | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | Jul. 19, 2013 | |
| Application notes | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | Sep. 10, 2010 | |
| User guides | ADS61x9/55xxEVM User's Guide (Rev B of the EVM board) (Rev. A) | Jun. 11, 2009 | |
| Application notes | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | Apr. 28, 2009 | |
| Application notes | CDCE62005 as Clock Solution for High-Speed ADCs | Sep. 04, 2008 | |
| Application notes | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | Jun. 08, 2008 | |
| Application notes | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | Jun. 02, 2008 | |
| Application notes | QFN Layout Guidelines | Jul. 28, 2006 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADS6125EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS6125 device, a low power 12-bit 125 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible environment to (...)
Features
- Transformer coupled analog input path
- Transformer coupled clock input path
- Amplifier path based on the THS4509
- Configurable parallel output modes
- Direct connection to TSW1100 High Speed ADC Capture Card
- Separate analog and digital supply connections
Description
The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instrumentsâ (TI) most popular high speed analog-to-digital converters (ADC).
ÂThe TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)
Features
Software development
Design tools & simulation
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| VQFN (RGZ) | 48 | View options |
Ordering & quality
Support & training
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Training series
View all TI training and videosVideos
Hands-on Experiment – System Power Scaling
This hands-on experiment shows the impact that ADC sampling rate has on the system power consumption.
