SLWU095 april   2023

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Functionality
    1. 2.1 ADC EVM Data Capture
    2. 2.2 DAC EVM Pattern Generator
  5. 3Hardware Configuration
    1. 3.1 Power Connections
    2. 3.2 Switches, Jumpers, and LEDs
      1. 3.2.1 Switches and Push-Buttons
      2. 3.2.2 Jumpers
    3. 3.3 LEDs
      1. 3.3.1 Power and Configuration LEDs
      2. 3.3.2 Spare LEDs
      3. 3.3.3 Connectors
        1. 3.3.3.1 SMA Connectors
        2. 3.3.3.2 FPGA Mezzanine Card (FMC+) Connector
        3. 3.3.3.3 JTAG Connectors
        4. 3.3.3.4 USB3.0 I/O Connection
  6. 4Software Start-Up
    1. 4.1 Installation Instructions
    2. 4.2 USB Interface and Drivers
  7. 5Downloading Firmware

3.3.3.1 SMA Connectors

The TSW14J59 has 5 SMA connectors. Table 3-4 defines the connectors:

Table 3-4 SMA Connectors
ComponentConnectorDescription
J31SYNCA3.3V or 1.8V CMOS logic SYNC output from FPGA pin F22. A shunt on pins 1–2 of J21 sets the level to 3.3V (default).

A shunt on pins 2-3 sets the level to 1.8V.

J32SYNCB3.3V or 1.8V CMOS logic SYNC output from FPGA pin G22. A shunt on pins 1–2 of J21 sets the level to 3.3V (default).

A shunt on pins 2-3 sets the level to 1.8V.

J33SYNCC3.3V or 1.8V CMOS logic SYNC output from FPGA pin M24. A shunt on pins 1–2 of J21 sets the level to 3.3V (default).

A shunt on pins 2-3 sets the level to 1.8V.

J36TRIG IN A3.3V or 1.8V CMOS logic trigger input to FPGA pin E26. A shunt on pins 1–2 of J21 sets the level to 3.3V (default).

A shunt on pins 2-3 sets the level to 1.8V.

J43TRIG IN B3.3V or 1.8V CMOS logic trigger input to FPGA pin L23. A shunt on pins 1-2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V.
Note: SYNCA, SYNCB, and SYNCC SMAs are used to provide external SYNC signals from the FPGA. The cables of each SYNC signal have equal length to verify the signal arrives at the same time for all boards using these SYNCs. The TRIG IN A/B SMA connectors can be used to trigger the FPGA from an external source. All five SMAs can use either 3.3V or 1.8V logic CMOS signals. By default, the EVM is setup for 3.3V logic levels. The EVM has on-board translators to set these inputs/outputs to the correct voltage levels for the FPGA.