SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

1.1 Clocking Scheme

The LMK5XXXXXS1 is configured to provide differential 125MHz network timing PTP clock to the syn1588® Time-of-Day clock in the LVDS output format. The 125MHz frequency and phase is adjusted digitally using the built-in DCO function of the digital phase-locked loop (DPLL) in the network synchronizer. The reference input frequencies of the DPLL are configured as 10MHz and 156.25MHz. The 10MHz signal is externally generated by an OCXO or a Rubidium stable lab reference clock and takes priority over the 156.25MHz signal, which is a PHY recovered clock frequency that is derived from the 10G Ethernet transceivers.

The 156.25MHz recovered PHY clock signal is extracted from the PCS modules and supplied to the DPLL reference input of the LMK5XXXXXS1 in LVDS format. If the PTP device, which provides the time information, can provide a sufficiently stable carrier frequency for SyncE, then the 156.25MHz clock is selected as the primary reference for the PTP DPLL within the LMK5XXXXXS1.

Figure 1-2 provides a block diagram of the LMK5XXXXXS1 configuration. The digital frequency adjustment, as well as the input and output clock configuration, of the network synchronizer can be tested using the corresponding TICS Pro profile of the LMK5XXXXXS1. The register configuration of the LMK5XXXXXS1 can be visualized using the TICS Pro software as depicted in Figure 1-4.

LMK5XXXXXS1 Input and Output Clock Configuration OverviewFigure 1-2 LMK5XXXXXS1 Input and Output Clock Configuration Overview

The DCO is enabled for the DPLL loop to phase and frequency steer the output clock, as required for IEEE-1588 PTP. The desired frequency step size has a frequency accuracy of a parts-per-trillion (ppt). A more detailed overview depicting the interconnection between DPLL2 and APLL2 is shown in Figure 1-3. The TICS Pro configuration of DPLL2 and APLL2 is represented in Figure 1-4.

DPLL and APLL in the LMK5XXXXXS1 Block DiagramFigure 1-3 DPLL and APLL in the LMK5XXXXXS1 Block Diagram
DPLL ConfigurationFigure 1-4 DPLL Configuration

For compliance testing purposes, only one differential output port, OUT7, is enabled in LVDS mode as shown in Figure 1-5. The network synchronizer device parameters are loaded into the control registers at startup via SPI or I2C.

Frequency Output ConfigurationFigure 1-5 Frequency Output Configuration