SNAA365 June   2024 LMK5B33216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Hardware Architecture
    1. 1.1 Clocking Scheme
    2. 1.2 FPGA Design
  5. 2syn1588® Synchronization Algorithm
    1. 2.1 PTP Time-of-Day Clock Adjustment Algorithm
  6. 3Test Setup
    1. 3.1 FMC Adapter Board
    2. 3.2 Compliance Test Setup
    3. 3.3 Compliance Test of Telecom Profile G.8275.1 - Full Timing Support
      1. 3.3.1 Transfer Characteristic
      2. 3.3.2 Absolute Time Error
      3. 3.3.3 Lock Time
    4. 3.4 Compliance Test of Telecom Profile G.8275.2 - Partial Timing Support
    5. 3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient
  7. 4PTP System Application
  8. 5Additional Development
  9. 6Conclusion
  10. 7References

3.5 Compliance Test of Telecom Profile G.8262.1 - SyncE Transient

The short-term transient response refers to the time accuracy error occurring when a clock switches over from one input reference to another. A reference switch over must adhere to the limits and conditions for SyncE short term transients as described in G.8262.1

The resulting graphs are shown in Figure 3-15 and Figure 3-16.

SyncE Transient TIE Figure 3-15 SyncE Transient TIE
SyncE Transient MTIE Figure 3-16 SyncE Transient MTIE