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LMK5B33216

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16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO

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Data sheet

LMK5B33216

ACTIVE
Data sheet Order now

Product details

Function Clock network synchronizer Number of outputs 16 RMS jitter (fs) 47 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Output type CML, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features JESD204B Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 16 RMS jitter (fs) 47 Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Output type CML, LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Features JESD204B Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGC) 64 81 mm² 9 x 9
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz
    • 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz

  • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
    • < 1-ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1-Hz (1-PPS) to 800-MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS/LVPECL, LVDS and HSCL output formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs
    • 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI interface
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz
    • 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz

  • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)

    • Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
    • < 1-ppt DCO frequency adjustment step size
  • 2 differential or single-ended DPLL inputs
    • 1-Hz (1-PPS) to 800-MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS/LVPECL, LVDS and HSCL output formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs
    • 1-Hz (1-PPS) to 1250-MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C or 3-wire/4-wire SPI interface

The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D).

The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 312.5 MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and phase buildout may be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D).

The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 312.5 MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and phase buildout may be enabled to control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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* Data sheet LMK5B33216 3-DPLL, 3-APLL, 2-IN, 16-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications datasheet (Rev. B) PDF | HTML 21 Jul 2022
User guide LMK5B33216 Programmer's Guide (Rev. A) PDF | HTML 11 Jul 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK5B33216EVM — LMK5B33216 evaluation module for 16-output, three DPLL and APLL, network synchronizer with BAW VCO

The LMK5B33216 evaluation module (EVM) is a platform for developing the LMK5B33216 network clock generator and synchronizer. The EVM can be used for device evaluation, compliance testing and system prototyping.

LMK5B33216EVM integrates three analog phase-locked loops (APLLs) and three digital PLLs (...)

User guide: PDF | HTML
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Application software & framework

PLLATINUMSIM-SW — Texas Instruments PLLatinum Simulator Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
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Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
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Simulation model

LMK5B33216 IBIS model

SNAM252.ZIP (167 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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