SNAS512L September   2011  – April 2026 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Unless otherwise specified: Vcc = 3.3V ± 5%, Vcco = 3.3V ± 5%, 2.5V ± 5%, -40°C ≤ TA ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3V/ns. Typical values represent most likely parametric norms at Vcc = 3.3V, Vcco = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION(2)
ICC_CORE Core Supply Current, All Outputs Disabled CLKinX selected 8.5 10.5 mA
OSCin selected 10 13.5 mA
ICC_PECL Additive Core Supply Current, Per LVPECL Bank Enabled 20 27 mA
ICC_LVDS Additive Core Supply Current, Per LVDS Bank Enabled LMK00301 26 32.5 mA
LMK00301A 31 38
ICC_HCSL Additive Core Supply Current, Per HCSL Bank Enabled 35 42 mA
ICC_CMOS Additive Core Supply Current, LVCMOS Output Enabled 3.5 5.5 mA
ICCO_PECL Additive Output Supply Current, Per LVPECL Bank Enabled Includes Output Bank Bias and Load Currents,
RT = 50Ω to Vcco - 2V on all outputs in bank		 165 197 mA
ICCO_LVDS Additive Output Supply Current, Per LVDS Bank Enabled LMK00301 34 44.5 mA
LMK00301A 24 33.5
ICCO_HCSL Additive Output Supply Current, Per HCSL Bank Enabled Includes Output Bank Bias and Load Currents,
RT = 50Ω on all outputs in bank		 Vcco = 3.3V ± 5% 87 104 mA
Vcco = 2.5V ± 5%
ICCO_CMOS Additive Output Supply Current, LVCMOS Output Enabled 200MHz, CL = 5pF Vcco = 3.3V ± 5% 9 10 mA
Vcco = 2.5V ± 5% 7 8 mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRRPECL Ripple-Induced
Phase Spur Level(3)
Differential LVPECL Output		 100kHz, 100mVpp Ripple Injected on Vcco,
Vcco = 2.5V		 156.25MHz -65 dBc
312.5MHz -63
PSRRHCSL Ripple-Induced
Phase Spur Level(3)
Differential HCSL Output		 156.25MHz -76 dBc
312.5MHz -74
PSRRLVDS Ripple-Induced
Phase Spur Level(3)
Differential LVDS Output		 156.25MHz -72 dBc
312.5MHz -63
CMOS CONTROL INPUTS (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
VIH High-Level Input Voltage 1.6 Vcc V
VIL Low-Level Input Voltage GND 0.4 V
IIH High-Level Input Current VIH = Vcc, Internal pull-down resistor 50 µA
IIL Low-Level Input Current VIL = 0V, Internal pull-down resistor -5 0.1 µA
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKin Input Frequency Range(10) Functional up to 3.1GHz
Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications)		 DC 3.1 GHz
VIHD Differential Input High Voltage CLKin driven differentially Vcc V
VILD Differential Input Low Voltage GND V
VID Differential Input Voltage Swing(4) 0.15 1.3 V
VCMD Differential Input Common Mode Voltage VID = 150mV 0.25 Vcc - 1.2 V
VID = 350mV 0.25 Vcc - 1.1
VID = 800mV 0.25 Vcc - 0.9
VIH Single-Ended Input High Voltage CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range Vcc V
VIL Single-Ended Input Low Voltage GND V
VI_SE Single-Ended Input Voltage Swing(15)(17) 0.3 2 Vpp
VCM Single-Ended Input Common Mode Voltage 0.25 Vcc - 1.2 V
ISOMUX Mux Isolation, CLKin0 to CLKin1 fOFFSET > 50kHz,
PCLKinX = 0dBm		 fCLKin0 = 100MHz -84 dBc
fCLKin0 = 200MHz -82
fCLKin0 = 500MHz -71
fCLKin0 = 1000MHz -65
CRYSTAL INTERFACE (OSCin, OSCout)
FCLK External Clock Frequency Range(10) OSCin driven single-ended, OSCout floating 250 MHz
FXTAL Crystal Frequency Range Fundamental mode crystal
ESR ≤ 200Ω (10 to 30MHz)
ESR ≤ 125Ω (30 to 40MHz)(5)		 10 40 MHz
CIN OSCin Input Capacitance 4 pF
LVPECL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FS Maximum Output Frequency Full VOD Swing(10)(11) VOD ≥ 600mV,
RL = 100Ω differential		 Vcco = 3.3V ± 5%,
RT = 160Ω to GND		 1.0 1.2 GHz
Vcco = 2.5V ± 5%,
RT = 91Ω to GND		 0.75 1.0
fCLKout_RS Maximum Output Frequency Reduced VOD Swing(10)(11) VOD ≥ 400mV,
RL = 100Ω differential		 Vcco = 3.3V ± 5%,
RT = 160Ω to GND		 1.5 3.1 GHz
Vcco = 2.5V ± 5%,
RT = 91Ω to GND		 1.5 2.3
JitterADD Additive RMS Jitter, Integration Bandwidth
10kHz to 20MHz(15)(6)(16)		 Vcco = 2.5V ± 5%:
RT = 91Ω to GND,
Vcco = 3.3V ± 5%:
RT = 160Ω to GND,
RL = 100Ω differential		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 77 98 fs
CLKin: 156.25MHz,
Slew rate ≥ 3V/ns		 54 78
JitterADD Additive RMS Jitter Integration Bandwidth
1MHz to 20MHz(6)		 Vcco = 3.3V,
RT = 160Ω to GND,
RL = 100Ω differential		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 59 fs
CLKin: 156.25MHz, Slew rate ≥ 2.7V/ns 64
CLKin: 625MHz,
Slew rate ≥ 3V/ns		 30
JitterADD Additive RMS Jitter with LVPECL clock source from LMK03806(6)(7) Vcco = 3.3V,
RT = 160Ω to GND,
RL = 100Ω differential		 CLKin: 156.25MHz, JSOURCE = 190 fs RMS (10kHz to 1MHz) 20 fs
CLKin: 156.25MHz, JSOURCE = 195 fs RMS (12kHz to 20MHz) 51
Noise Floor Noise Floor
fOFFSET ≥ 10MHz(8)(9)		 Vcco = 3.3V,
RT = 160Ω to GND,
RL = 100Ω differential		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 -162.5 dBc/Hz
CLKin: 156.25MHz, Slew rate ≥ 2.7V/ns -158.1
CLKin: 625MHz,
Slew rate ≥ 3V/ns		 -154.4
DUTY Duty Cycle(10) 50% input clock duty cycle 45% 55%
VOH Output High Voltage TA = 25°C, DC Measurement,
RT = 50Ω to Vcco - 2V		 Vcco - 1.2 Vcco - 0.9 Vcco - 0.7 V
VOL Output Low Voltage Vcco - 2.0 Vcco - 1.75 Vcco - 1.5 V
VOD Output Voltage Swing(4) 600 830 1000 mV
tR Output Rise Time
20% to 80%(15)		 RT = 160Ω to GND, Uniform transmission line up to 10 in. with 50Ω characteristic impedance,
RL = 100Ω differential, CL ≤ 5pF		 175 300 ps
tF Output Fall Time
80% to 20%(15)		 175 300 ps
LVDS OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout_FS Maximum Output Frequency
Full VOD Swing(10)(11)		 VOD ≥ 250mV,
RL = 100Ω differential		 1.0 1.6 GHz
fCLKout_RS Maximum Output Frequency
Reduced VOD Swing(10)(11)		 VOD ≥ 200mV,
RL = 100Ω differential		 1.5 2.1 GHz
JitterADD Additive RMS Jitter,
Integration Bandwidth
10kHz to 20MHz(15)(6)(16)		 RL = 100Ω differential CLKin: 100MHz,
Slew rate ≥ 3V/ns		 94 115 fs
CLKin: 156.25MHz,
Slew rate ≥ 3V/ns		 70 90
JitterADD Additive RMS Jitter
Integration Bandwidth
1MHz to 20MHz(6)		 Vcco = 3.3V,
RL = 100Ω differential		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 89 fs
CLKin: 156.25MHz,
Slew rate ≥ 2.7V/ns		 77
CLKin: 625MHz,
Slew rate ≥ 3V/ns		 37
Noise Floor Noise Floor
fOFFSET ≥ 10MHz(8)(9)		 Vcco = 3.3V,
RL = 100Ω differential		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 -159.5 dBc/Hz
CLKin: 156.25MHz,
Slew rate ≥ 2.7V/ns		 -157.0
CLKin: 625MHz,
Slew rate ≥ 3V/ns		 -152.7
DUTY Duty Cycle(10) 50% input clock duty cycle 45% 55%
VOD Output Voltage Swing(4) TA = 25°C, DC Measurement,
RL = 100Ω differential		 250 400 450 mV
ΔVOD Change in Magnitude of VOD for Complementary Output States -50 50 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS Change in Magnitude of VOS for Complementary Output States -35 35 mV
ISA
ISB		 Output Short Circuit Current Single Ended TA = 25°C,
Single ended outputs shorted to GND		 -24 24 mA
ISAB Output Short Circuit Current Differential Complementary outputs tied together -12 12 mA
tR Output Rise Time
20% to 80%(15)		 Uniform transmission line up to 10 inches with 50Ω characteristic impedance,
RL = 100Ω differential, CL ≤ 5pF		 175 300 ps
tF Output Fall Time
80% to 20%(15)		 175 300 ps
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout Output Frequency Range(10) RL = 50Ω to GND, CL ≤ 5pF DC 800 MHz
JitterADD_PCIe Additive RMS Phase Jitter for PCIe 7.04 PLL BW: 0.5 - 1MHz; CDR = 10MHz

2.79

6.28

10.1

 fs
Additive RMS Phase Jitter for PCIe 6.04 PLL BW: 0.5 - 1MHz; CDR = 10MHz CLKin: 100MHz,
Slew rate ≥ 2V/ns

4.00

8.99

14.3
Additive RMS Phase Jitter for PCIe 5.04 PCIe5.0 filter

3.64

12.9

23.6
Additive RMS Phase Jitter for PCIe 3.0(10) PCIe Gen 3,
PLL BW = 2–5MHz,
CDR = 10MHz		 CLKin: 100MHz,
Slew rate ≥ 0.6V/ns

15.9

 36.2

56.3
Additive RMS Phase Jitter for PCIe 4.0(4) PCIe Gen 4,
PLL BW = 2–5MHz,
CDR = 10MHz		 CLKin: 100MHz,
Slew rate ≥ 1.8V/ns

15.9

36.2

56.3
JitterADD Additive RMS Jitter
Integration Bandwidth
1MHz to 20MHz(6)		 Vcco = 3.3V,
RT = 50Ω to GND		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 77 fs
CLKin: 156.25MHz,
Slew rate ≥ 2.7V/ns		 86
Noise Floor Noise Floor
fOFFSET ≥ 10MHz(8)(9)		 Vcco = 3.3V,
RT = 50Ω to GND		 CLKin: 100MHz,
Slew rate ≥ 3V/ns		 -161.3 dBc/Hz
CLKin: 156.25MHz,
Slew rate ≥ 2.7V/ns		 -156.3
DUTY Duty Cycle(10) 50% input clock duty cycle CLKin ≤ 400MHz 45% 55%
VOH Output High Voltage RL = 50Ω to GND, CL ≤ 5pF CLKin<300MHZ

675

 920 mV

300≤CLKin<600MHz

600

920

CLKin≥600MHz

520

920
RL = 50Ω to GND, CL ≤ 5pF -150 0.5 150
VOL Output Low Voltage mV

Current Source varation

HCSL current source variation

 RL = 50Ω to GND, CL ≤ 5pF

14

15

17

mA
VCROSS Absolute Crossing Voltage
(10)(12)		 RL = 50Ω to GND, CL ≤ 5pF CLKin ≤ 400MHz 160 350 460 mV
ΔVCROSS Total Variation of VCROSS
(10)(12)		 140 mV
tR Output Rise Time
20% to 80%(15)(12)		 250MHz, Uniform transmission line up to 10 inches with 50Ω characteristic impedance,
RL = 50Ω to GND, CL ≤ 5pF		 300 500 ps
tF Output Fall Time
80% to 20%(15)(12)		 300 500 ps
LVCMOS OUTPUT (REFout)
fCLKout Output Frequency Range(10) CL ≤ 5pF DC 250 MHz
JitterADD Additive RMS Jitter
Integration Bandwidth
1MHz to 20MHz(6)		 Vcco = 3.3V, CL ≤ 5pF 100MHz, Input Slew rate ≥ 3V/ns 95 fs
Noise Floor Noise Floor
fOFFSET ≥ 10MHz(8)(9)		 Vcco = 3.3V, CL ≤ 5pF 100MHz, Input Slew rate ≥ 3V/ns -159.3 dBc/Hz
DUTY Duty Cycle(10) 50% input clock duty cycle 45% 55%
VOH Output High Voltage 1mA load Vcco - 0.1 V
VOL Output Low Voltage 0.1 V
IOH Output High Current (Source) Vo = Vcco / 2 Vcco = 3.3V 28 mA
Vcco = 2.5V 20
IOL Output Low Current (Sink) Vcco = 3.3V 28 mA
Vcco = 2.5V 20
tR Output Rise Time
20% to 80%(15)(12)		 250MHz, Uniform transmission line up to 10 inches with 50Ω characteristic impedance,
RL = 50Ω to GND, CL ≤ 5pF		 225 400 ps
tF Output Fall Time
80% to 20%(15)(12)		 225 400 ps
tEN Output Enable Time(13) CL ≤ 5pF 3 cycles
tDIS Output Disable Time(13) 3 cycles
PROPAGATION DELAY and OUTPUT SKEW
tPD_PECL Propagation Delay
CLKin-to-LVPECL(15)		 RT = 160Ω to GND, RL = 100Ω differential, CL ≤ 5pF 180 360 540 ps
tPD_LVDS Propagation Delay
CLKin-to-LVDS(15)		 RL = 100Ω differential, CL ≤ 5pF 200 400 600 ps
tPD_HCSL Propagation Delay
CLKin-to-HCSL(15)(12)		 RT = 50Ω to GND, CL ≤ 5pF 295 590 885 ps
tPD_CMOS Propagation Delay
CLKin-to-LVCMOS(15)(12)		 CL ≤ 5pF Vcco = 3.3V 900 1475 2300 ps
Vcco = 2.5V 1000 1550 2700
tSK(O) Output Skew
LVPECL/LVDS/HCSL
(10)(12)(14)		 Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications. 30 50 ps
tSK(PP) Part-to-Part Output Skew LVPECL/LVDS/HCSL
(15)(12)(14)		 80 120 ps
(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions or Notes. Typical specifications are estimations only and are not ensured.
(2) See Power Supply Recommendations for more information on current consumption and power dissipation calculations. Characteristics for both LMK00301 and LMK00301A are the same unless specified under the test conditions.
(3) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(PSRR / 20)) / (π × fCLK) ] × 1E12
(4) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(5) The ESR requirements stated must be met to verify that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal can be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations.
(6) For the 100MHz and 156.25MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2×10dBc/10) / (2×π×fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10×log10(20MHz - 1MHz). The additive RMS jitter was approximated for 625MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Typical Characteristics.
(7) 156.25MHz LVPECL clock source from LMK03806 with 20MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). Typical JSOURCE = 190 fs RMS (10kHz to 1MHz) and 195 fs RMS (12kHz to 20MHz). Refer to the LMK03806 data sheet for more information.
(8) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10MHz, but for lower frequencies this measurement offset can be as low as 5MHz due to measurement equipment limitations.
(9) Phase noise floor degrades as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) is less susceptible to degradation in noise floor at lower slew rates due to the common mode noise rejection. Use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
(10) Specification is verified by characterization and is not tested in production.
(11) See Typical Characteristics for output operation over frequency.
(12) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
(13) Output Enable Time is the number of input clock cycles required for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles required for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal must have an edge transition much faster than that of the input clock period for accurate measurement.
(14) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.
(15) Parameter is specified by design, not tested in production.
(16) 100MHz and 156.25MHz input source from Rohde & Schwarz SMA100A Low-Noise Signal Generator and Sine-to-Square-wave Conversion block
(17) For clock input frequency ≥ 100MHz, CLKinX can be driven with single-ended (LVCMOS) input swing up to 3.3Vpp. For clock input frequency < 100MHz, the single-ended input swing must be limited to 2Vpp maximum to prevent input saturation (refer to Driving the Clock Inputs for interfacing 2.5V/3.3V LVCMOS clock input < 100MHz to CLKinX).