SNAS512L September   2011  – April 2026 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock Inputs
      2. 8.4.2 Clock Outputs
        1. 8.4.2.1 Reference Output
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
          1. 9.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 9.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 9.2.2.1.3 Termination for Single-Ended Operation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Sequencing
      2. 9.3.2 Current Consumption and Power Dissipation Calculations
        1. 9.3.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
        2. 9.3.2.2 Power Dissipation Example #2: Worst-Case Dissipation
      3. 9.3.3 Power Supply Bypassing
        1. 9.3.3.1 Power Supply Ripple Rejection
      4. 9.3.4 Thermal Management
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3.3.1 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, and so forth. While power supply bypassing can help filter out some of this noise, understanding the effect of power supply ripple on the device performance is important. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00301, the signal can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc).

For the LMK00301, power supply ripple rejection, or PSRR, is measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal is injected onto the VCCO supply. Figure 9-17 shows the PSRR test setup.

LMK00301 PSRR Test SetupFigure 9-17 PSRR Test Setup

A signal generator is used to inject a sinusoidal signal onto the VCCO supply of the DUT board, and the peak-to-peak ripple amplitude is measured at the VCCO pins of the device. A limiting amplifier is used to remove amplitude modulation on the differential output clock and convert the amplitude modulation to a single-ended signal for the phase noise analyzer. The phase spur level measurements are taken for clock frequencies of 156.25MHz and 312.5MHz under the following power supply ripple conditions:

  • Ripple amplitude: 100mVpp on VCCO = 2.5V
  • Ripple frequencies: 100kHz, 1MHz, and 10MHz

Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:

Equation 13. DJ (ps pk-pk) = [(2×10(PSRR / 20)) / (π×fCLK)] × 1012

The PSRR vs Ripple Frequency plots in Typical Characteristics show the ripple-induced phase spur levels for the differential output types at 156.25MHz and 312.5MHz . The LMK00301 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for LVPECL are below –64dBc at 156.25MHz and below –62dBc at 312.5MHz. Using Equation 13, these phase spur levels translate to Deterministic Jitter values of 2.57ps pk-pk at 156.25MHz and 1.62ps pk-pk at 312.5MHz. Testing has shown that the PSRR performance of the device improves for VCCO = 3.3V under the same ripple amplitude and frequency conditions.