SNAS635F December   2013  – August 2025 LMK00334

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Crystal Power Dissipation vs RLIM
      2. 7.3.2 Clock Inputs
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Reference Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC and VCCO Power Supplies
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Driving the Clock Inputs
        2. 8.2.1.2 Crystal Interface
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Termination and Use of Clock Drivers
        2. 8.2.2.2 Termination for DC-Coupled Differential Operation
        3. 8.2.2.3 Termination for AC-Coupled Differential Operation
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Current Consumption and Power Dissipation Calculations
        1. 8.3.1.1 Power Dissipation Example: Worst-Case Dissipation
      2. 8.3.2 Power Supply Bypassing
        1. 8.3.2.1 Power Supply Ripple Rejection
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Management
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

10 Revision History

Changes from Revision E (January 2022) to Revision F (August 2025)

  • Added PCIe Gen 6 and Gen 7 additive jitter specification to the Features sectionGo
  • Updated the PCIe Gen 3 to Gen 5 additive jitter specification in the Features sectionGo
  • Added PCIe Gen 6 and Gen 7 additive jitter specification to the Electrical Characteristics sectionGo
  • Updated the PCIe Gen 3 to Gen 5 additive jitter specification in the Electrical Characteristics sectionGo

Changes from Revision D (July 2021) to Revision E (January 2022)

  • Changed data sheet titleGo
  • Added links to the Applications sectionGo
  • Added text to the Description sectionGo
  • Added example board layout to Packaging Information section.Go

Changes from Revision C (July 2017) to Revision D (July 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added PCIe Gen 5.0 to the data sheetGo
  • Corrected PN in Figure 8-4 and Figure 8-5 to LMK00334.Go

Changes from Revision B (May 2017) to Revision C (July 2017)

  • Added PCIe 4.0 compliance dataGo

Changes from Revision A (October 2014) to Revision B (May 2017)

  • Changed CLKout_EN pin to CLKout_EN throughout the data sheetGo
  • Add pins 28 and 32 to the Pin Functions table Go
  • Moved the storage temperature to the Absolute Maximum Ratings tableGo
  • Added test conditions to the output supply voltage parameter in the Recommended Operating Conditions tableGo

Changes from Revision * (December 2013) to Revision A (October 2014)

  • Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information Go
  • Changed from 1MHz to 12kHz in Electrical Characteristics Go
  • Deleted "The additive jitter The additive RMS jitter was approximated ... "Go