SNAS815C December   2020  – February 2026 LMK1D1204 , LMK1D1208

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
    1. 4.1 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input and Hysteresis
      2. 8.3.2 Input Mux
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.2 Input Termination

The LMK1D120x input stage is designed with flexibility in mind to allow the user to drive the device with a wide variety of signal types. This device can be interfaced with LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS drivers. Please refer to the Electrical Characteristics for more details.

LVDS drivers can be connected to LMK1D120x inputs with DC- and AC-coupling as shown Figure 8-3 and Figure 8-4 (respectively).

LMK1D1204 LMK1D1208 LVDS Clock Driver Connected to LMK1D120x Input (DC-Coupled)Figure 8-3 LVDS Clock Driver Connected to LMK1D120x Input (DC-Coupled)
LMK1D1204 LMK1D1208 LVDS Clock Driver Connected to LMK1D120x Input (AC-Coupled)Figure 8-4 LVDS Clock Driver Connected to LMK1D120x Input (AC-Coupled)

Figure 8-5 shows how to connect LVPECL inputs to the LMK1D120x. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6VPP.

LMK1D1204 LMK1D1208 LVPECL Clock Driver Connected to LMK1D120x InputFigure 8-5 LVPECL Clock Driver Connected to LMK1D120x Input

Figure 8-6 illustrates how to couple a LVCMOS clock input to the LMK1D120x directly.

LMK1D1204 LMK1D1208 1.8V/2.5V/3.3V LVCMOS Clock Driver Connected to LMK1D120x InputFigure 8-6 1.8V/2.5V/3.3V LVCMOS Clock Driver Connected to LMK1D120x Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1kΩ resistors.