8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer


Product details


Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout, Universal inputs Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RHD) 28 25 mm² 5 x 5 open-in-new Find other Clock buffers


  • High-performance LVDS clock buffer family with 2 inputs and 4 (2:4) or 8 (2:8) outputs.
  • Output frequency up to 2 GHz.
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < maximum 60 fs RMS in 12-kHz to 20-MHz at 156.25 MHz
    • Very low phase noise floor: –164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, LP-HCSL, HCSL and CML inputs
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • LMK1D1204: 3-mm × 3-mm, 16-pin VQFN (RGT)

    • LMK1D1208: 5-mm × 5-mm, 28-pin VQFN (RHD)

open-in-new Find other Clock buffers


The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

The LMK1D12x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12x package variant is shown in the table below:

open-in-new Find other Clock buffers
Similar products you might be interested in
open-in-new Compare products
Same functionality with different pin-out to the compared device.
NEW LMK1D1204 ACTIVE 4-channel output LVDS 1.8-V buffer 4 outputs vs. 8 outputs

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet LMK1D120x Low Additive Jitter LVDS Buffer datasheet (Rev. A) Aug. 10, 2021
User guide LMK1D1208 Low-Additive Jitter, Eight LVDS Outputs Clock Buffer Evaluation Board Aug. 04, 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
LMK1D1208 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and eight LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1208. This EVM can also be used to evaluate other 28-pin devices within the (...)
  • Easy to use evaluation board to fan-out at least 4 LVDS clocks with low phase noise/jitter
  • Control pins configurable through jumper
  • Board powered from a single 3.3V / 2.5V / 1.8V supply

Design tools & simulation

SNAM250.ZIP (29 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RHD) 28 View options

Ordering & quality

Information included:
  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​