SNAS822C September   2021  – February 2026 LMK1D2102 , LMK1D2104

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 LMK1D2102: RGT Package 16-Pin VQFN Top View
Figure 5-2 LMK1D2104: RHD Package 28-Pin VQFN Top View
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMELMK1D2102LMK1D2104
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N6, 79, 10IPrimary: Differential input pair or single-ended input
IN1_P, IN1_N3, 45, 6ISecondary: Differential input pair or single-ended input.
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
OUTPUT BANK CONTROL
EN24IOutput bank enable/disable with an internal 500kΩ pullup and 320kΩ pulldown, selects input port; (See Table 8-1)
BIAS VOLTAGE OUTPUT
VAC_REF0,VAC_REF1811, 7OBias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N9, 1012, 13ODifferential LVDS output pair number 0
OUT1_P, OUT1_N11, 1216, 17ODifferential LVDS output pair number 1
OUT2_P, OUT2_N13, 1418, 19ODifferential LVDS output pair number 2
OUT3_P, OUT3_N15, 1620, 21ODifferential LVDS output pair number 3
OUT4_P, OUT4_N22, 23ODifferential LVDS output pair number 4
OUT5_P, OUT5_N24, 25ODifferential LVDS output pair number 5
OUT6_P, OUT6_N26, 27ODifferential LVDS output pair number 6
OUT7_P, OUT7_N2, 3 ODifferential LVDS output pair number 7
SUPPLY VOLTAGE
VDD58, 15, 28PDevice Power Supply (1.8V or 2.5V or 3.3V)
GROUND
GND11, 14GGround
DAPDAPDAP

G

Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
(1) G = Ground, I = Input, O = Output, P = Power