SNAS822C
September 2021 – February 2026
LMK1D2102
,
LMK1D2104
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Fail-Safe Inputs
8.4
Device Functional Modes
8.4.1
LVDS Output Termination
8.4.2
Input Termination
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
1
Features
High-performance LVDS clock buffer family: up to 2GHz
Dual 1:2 differential buffer
Dual 1:4 differential buffer
Supply voltage: 1.71V to 3.465V
Fail-safe input operation
Low additive jitter: < max 60fs RMS in 12kHz to
20MHz at 156.25MHz
Very low phase noise floor: -164dBc/Hz (typical)
Very low propagation delay < 575ps max
Output skew of 20ps max
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.
LVDS reference voltage, V
AC_REF
, available for capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
LMK1D2102
: 3mm × 3mm, 16-Pin VQFN
LMK1D2104
: 5mm × 5mm, 28-Pin VQFN