SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1 Device Registers

Table 7-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-1 must be considered as reserved locations and the register contents must not be modified.

Table 7-1 DEVICE Registers
Offset Acronym Register Name Section
0h R0 Powerdown and Reset Section 7.1.1
1h R1 Software reset, MUXOUT pin setting Section 7.1.2
2h R2 Channels, Logic Clock, SYSREF, SYNC and Temp Sensor Enable Section 7.1.3
3h R3 CLKIN Delay Section 7.1.4
4h R4 CLKOUT0 Enables, Power and Delay Section 7.1.5
5h R5 CLKOUT1 Enables, Power and Delay Section 7.1.6
6h R6 CLKOUT2 Enables, Power and Delay Section 7.1.7
7h R7 CLKOUT3 Enables, Power and Delay Section 7.1.8
8h R8 SYSREFOUT0 Enables, Power, VCM Section 7.1.9
9h R9 SYSREFOUT1 Enables, Power, VCM Section 7.1.10
Ah R10 SYSREFOUT2 Enables, Power, VCM Section 7.1.11
Bh R11 SYSREFOUT3 Enables, Power, VCM Section 7.1.12
Ch R12 LOGICLK Enables, Power, VCM and Output Formats Section 7.1.13
Dh R13 LOGISYSREF Enables, Power, VCM and Output Formats Section 7.1.14
Eh R14 LOGICLK Dividers Section 7.1.15
Fh R15 LOGICLK2 Enables, Dividers Section 7.1.16
10h R16 SYSREFREQ Input Section 7.1.17
11h R17 SYSREFREQ Input Section 7.1.18
12h R18 SYSREFREQ Input Section 7.1.19
13h R19 SYSREF Output Section 7.1.20
14h R20 SYSREF Output Dividers Section 7.1.21
15h R21 SYSREFOUT0 Delay Section 7.1.22
16h R22 SYSREFOUT1 Delay Section 7.1.23
17h R23 SYSREFOUT2 Delay Section 7.1.24
18h R24 SYSREFOUT3 Delay Section 7.1.25
19h R25 LOGISYSREFOUT Delay Section 7.1.26
1Ah R26 State Machine Clock Section 7.1.27
1Bh R27 Clock MUX, Clock Dividers/Multiplier Section 7.1.28
1Dh R29 SYSREFREQ Windowing (readback) Section 7.1.29
1Eh R30 SYSREFREQ Windowing (readback) Section 7.1.30
1Fh R31 Temperature Sensor (readback) Section 7.1.31
20h R32 Device Version ID (readback) Section 7.1.32
24h R36 Multiplier Mode (Reserved)
25h R37 Lock Detect (readback) Section 7.1.34
27h R39 Multiplier Mode (Reserved)
28h R40 Multiplier Mode (Reserved)
29h R41 Multiplier Mode (Reserved)
2Ah R42 Multiplier Mode (Reserved)
2Bh R43 Multiplier Mode (Reserved)
2Ch R44 Multiplier Mode (Reserved)
2Dh R45 Multiplier Mode (Reserved)
36h R54 Multiplier Mode (Reserved)
37h R55 Current Optimization Section 7.1.43
4Dh R77 Multiplier Mode (Reserved)

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for access types in this section.

Table 7-2 Device Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.1.1 R0 Register (Offset = 0h) [Reset = 0000h]

R0 is shown in Table 7-3.

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Table 7-3 R0 Register Field Descriptions
Bit Field Type Reset Description
15-2 UNDISCLOSED R 0h Program this field to 0x0.
1 POWERDOWN R/W 0h Sets the device in a low-power state. The states of other registers are maintained.
0 RESET R/W 0h Soft Reset. Resets the entirie logic and reigsters (equivalent to power-on reset). Self-clearing on next register write.

7.1.2 R1 Register (Offset = 1h) [Reset = 000Ah]

R1 is shown in Table 7-4.

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Table 7-4 R1 Register Field Descriptions
Bit Field Type Reset Description
15-5 UNDISCLOSED R/W 0h Program this field to 0x0.
4 LD_DIS R/W 0h If set to 0x1, disables the lock detect status coming out at MUXOUT pin in multiplier mode.
This bit must be set to 1, when interfacing multiple devices and wants to perform a readback operation in multiplier mode.
  • 0h = Lock Detect
  • 1h = Readback
3 READBACK_CTRL R/W 1h Set this field to 0x1 to readback the written register values. Set this field to 0x0 to readback the value set by device internal state machine.
2-0 UNDISCLOSED R/W 2h Program this field to 0x2.

7.1.3 R2 Register (Offset = 2h) [Reset = 00BFh]

R2 is shown in Table 7-5.

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Table 7-5 R2 Register Field Descriptions
Bit Field Type Reset Description
15-10 UNDISCLOSED R 0h Program this field to 0x0.
9 TEMPSENSE_EN R/W 0h Temperature sensor enable override bit
8 SYNC_EN R/W 0h Enables synchronization path for the dividers and allows the clock position capture circuitry to be enabled. Used for multi-device synchronization. Redundant if SYSREF_EN = 0x1.
7 UNDISCLOSED R/W 1h Program this field to 0x1.
6 SYSREF_EN R/W 0h Enables SYSREF subsystem (and SYNC subsystem when SYSREFREQ_MODE = 0x0). Setting this bit to 0x0 completely disables all SYNC, SYSREF, and clock position capture circuitry, overriding the state of other powerdown/enable bits except SYNC_EN. If SYNC_EN = 0x1, the SYNC path and clock position capture circuitry are still enabled, regardless of the state of SYSREF_EN.
5 UNDISCLOSED R/W 1h Program this field to 0x1.
4 LOGIC_EN R/W 1h Enables LOGICLK subsystem (LOGICLKOUT, LOGISYSREFOUT). Setting this bit to 0x0 completely disables all LOGICLKOUT and LOGISYSREFOUT circuitry, overriding the state of other powerdown/enable bits.
3 CH3_EN R/W 1h Enables CH3 (CLKOUT3, SYSREFOUT3). Setting this bit to 0 completely disables CH3, overriding the state of other powerdown/enable bits.
2 CH2_EN R/W 1h Enables CH2 (CLKOUT2, SYSREFOUT2). Setting this bit to 0 completely disables CH2, overriding the state of other powerdown/enable bits.
1 CH1_EN R/W 1h Enables CH1 (CLKOUT1, SYSREFOUT1). Setting this bit to 0 completely disables CH1, overriding the state of other powerdown/enable bits.
0 CH0_EN R/W 1h Enables CH0 (CLKOUT0, SYSREFOUT0). Setting this bit to 0 completely disables CH0, overriding the state of other powerdown/enable bits.

7.1.4 R3 Register (Offset = 3h) [Reset = 0000h]

R3 is shown in Table 7-6.

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Table 7-6 R3 Register Field Descriptions
Bit Field Type Reset Description
15-7 UNDISCLOSED R/W 0h Program this field to 0x0.
6-0 CLKIN_DLY R/W 0h Sets the delay at input clock. Delay range - 60ps and step size - 1.1ps

7.1.5 R4 Register (Offset = 4h) [Reset = 000Dh]

R4 is shown in Table 7-7.

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Table 7-7 R4 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R/W 0h Program this field to 0x0.
10-4 CLK0_DLY R/W 0h Sets the delay at CLKOUT0 output clock. Delay range - 55ps and step size - 0.9ps
3-1 CLK0_PWR R/W 6h Sets the output power of CLKOUT0. Larger values correspond to higher output power.
0 CLK0_EN R/W 1h Enables CLKOUT0 output buffer.

7.1.6 R5 Register (Offset = 5h) [Reset = 000Dh]

R5 is shown in Table 7-8.

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Table 7-8 R5 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R/W 0h Program this field to 0x0.
10-4 CLK1_DLY R/W 0h Sets the delay at CLKOUT1 output clock. Delay range - 55ps and step size - 0.9ps
3-1 CLK1_PWR R/W 6h Sets the output power of CLKOUT1. Larger values correspond to higher output power.
0 CLK1_EN R/W 1h Enables CLKOUT1 output buffer.

7.1.7 R6 Register (Offset = 6h) [Reset = 000Dh]

R6 is shown in Table 7-9.

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Table 7-9 R6 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R/W 0h Program this field to 0x0.
10-4 CLK2_DLY R/W 0h Sets the delay at CLKOUT2 output clock. Delay range - 55ps and step size - 0.9ps
3-1 CLK2_PWR R/W 6h Sets the output power of CLKOUT2. Larger values correspond to higher output power.
0 CLK2_EN R/W 1h Enables CLKOUT2 output buffer.

7.1.8 R7 Register (Offset = 7h) [Reset = 000Dh]

R7 is shown in Table 7-10.

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Table 7-10 R7 Register Field Descriptions
Bit Field Type Reset Description
15-11 UNDISCLOSED R/W 0h Program this field to 0x0.
10-4 CLK3_DLY R/W 0h Sets the delay at CLKOUT3 output clock. Delay range - 55ps and step size - 0.9ps
3-1 CLK3_PWR R/W 6h Sets the output power of CLKOUT3. Larger values correspond to higher output power.
0 CLK3_EN R/W 1h Enables CLKOUT3 output buffer.

7.1.9 R8 Register (Offset = 8h) [Reset = 5CA9h]

R8 is shown in Table 7-11.

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Table 7-11 R8 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R/W 0h Program this field to 0x0.
14 SYSREF0_PWR_LOW R/W 1h Sets the SYSREFOUT0 output deriver at low power. Set to value 0 for single ended higher swing.
13 SYSREF0_AC R/W 0h Enables SYSREFOUT0 AC coupled mode.
12-10 UNDISCLOSED R/W 7h Program this field to 0x7.
9-4 SYSREF0_VCM R/W Ah Sets the output common mode of SYSREFOUT0 with 25mV step size.
SYSREF0_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 SYSREF0_PWR R/W 4h Sets the output power of SYSREFOUT0. Larger values corespond to higher output power. SYSREFOUT0_VCM must be set properly to bring the output common mode voltage within permissible limits.
0 SYSREF0_EN R/W 1h Enables SYSREFOUT0 output buffer.

7.1.10 R9 Register (Offset = 9h) [Reset = 5CA9h]

R9 is shown in Table 7-12.

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Table 7-12 R9 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R/W 0h Program this field to 0x0.
14 SYSREF1_PWR_LOW R/W 1h Sets the SYSREFOUT1 output deriver at low power. Set to value 0 for single ended higher swing.
13 SYSREF1_AC R/W 0h Enables SYSREFOUT1 AC coupled mode.
12-10 UNDISCLOSED R/W 7h Program this field to 0x7.
9-4 SYSREF1_VCM R/W Ah Sets the output common mode of SYSREFOUT1 with 25mV step size.
SYSREF1_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 SYSREF1_PWR R/W 4h Sets the output power of SYSREFOUT1. Larger values corespond to higher output power. SYSREFOUT1_VCM must be set properly to bring the output common mode voltage within permissible limits.
0 SYSREF1_EN R/W 1h Enables SYSREFOUT1 output buffer.

7.1.11 R10 Register (Offset = Ah) [Reset = 5CA9h]

R10 is shown in Table 7-13.

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Table 7-13 R10 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R/W 0h Program this field to 0x0.
14 SYSREF2_PWR_LOW R/W 1h Sets the SYSREFOUT2 output deriver at low power. Set to value 0 for single ended higher swing.
13 SYSREF2_AC R/W 0h Enables SYSREFOUT2 AC coupled mode.
12-10 UNDISCLOSED R/W 7h Program this field to 0x7.
9-4 SYSREF2_VCM R/W Ah Sets the output common mode of SYSREFOUT2 with 25mV step size.
SYSREF2_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 SYSREF2_PWR R/W 4h Sets the output power of SYSREFOUT2. Larger values corespond to higher output power. SYSREFOUT2_VCM must be set properly to bring the output common mode voltage within permissible limits.
0 SYSREF2_EN R/W 1h Enables SYSREFOUT2 output buffer.

7.1.12 R11 Register (Offset = Bh) [Reset = 5CA9h]

R11 is shown in Table 7-14.

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Table 7-14 R11 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R/W 0h Program this field to 0x0.
14 SYSREF3_PWR_LOW R/W 1h Sets the SYSREFOUT3 output deriver at low power. Set to value 0 for single ended higher swing.
13 SYSREF3_AC R/W 0h Enables SYSREFOUT3 AC coupled mode.
12-10 UNDISCLOSED R/W 7h Program this field to 0x7.
9-4 SYSREF3_VCM R/W Ah Sets the output common mode of SYSREFOUT3 with 25mV step size.
SYSREF3_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 SYSREF3_PWR R/W 4h Sets the output power of SYSREFOUT3. Larger values corespond to higher output power. SYSREFOUT3_VCM must be set properly to bring the output common mode voltage within permissible limits.
0 SYSREF3_EN R/W 1h Enables SYSREFOUT3 output buffer.

7.1.13 R12 Register (Offset = Ch) [Reset = 002Bh]

R12 is shown in Table 7-15.

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Table 7-15 R12 Register Field Descriptions
Bit Field Type Reset Description
15-13 UNDISCLOSED R/W 0h Program this field to 0x0.
12-11 LOGICLK_FMT R/W 0h Selects the output driver format of the LOGICLKOUT output.
  • 0h = LVDS
  • 1h = Reserved
  • 2h = CML
  • 3h = Reserved
10-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-4 LOGICLK_VCM R/W 2h Sets the output common mode voltage of LOGICLKOUT in LVDS output format.
LOGICLK_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 LOGICLK_PWR R/W 5h Sets the output power of LOGICLKOUT.
Larger values correspond to higher output power.
0 LOGICLK_EN R/W 1h Enables the logic clock output buffer.

7.1.14 R13 Register (Offset = Dh) [Reset = 002Bh]

R13 is shown in Table 7-16.

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Table 7-16 R13 Register Field Descriptions
Bit Field Type Reset Description
15-13 UNDISCLOSED R/W 0h Program this field to 0x0.
12-11 LOGISYSREF_FMT R/W 0h Selects the output driver format of the LOGISYSREFOUT output.
  • 0h = LVDS
  • 1h = Reserved
  • 2h = CML
  • 3h = Reserved
10-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-4 LOGISYSREF_VCM R/W 2h Sets the output common mode voltage of LOGISYSREFOUT in LVDS output format.
LOGISYSREF_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
3-1 LOGISYSREF_PWR R/W 5h Sets the output power of LOGISYSREFOUT.
Larger values correspond to higher output power.
0 LOGISYSREF_EN R/W 1h Enables the logic SYSREF output buffer.

7.1.15 R14 Register (Offset = Eh) [Reset = 0084h]

R14 is shown in Table 7-17.

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Table 7-17 R14 Register Field Descriptions
Bit Field Type Reset Description
15 LOGICLK_DIV_RST R/W 0h Manual reset for logic clock divider.
14-13 UNDISCLOSED R/W 0h Program this field to 0x0.
12-3 LOGICLK_DIV R/W 10h Sets LOGICLK divider value. Maximum input frequency from LOGICLK_DIV_PRE must be ≤ 3200MHz. The maximum LOGICLKOUT frequency must be ≤ 800MHz to avoid amplitude degradation.
  • 0h = Reserved
  • 1h = Reserved
  • 2h = /2
  • 3h = /3
  • 3FFh = /1023
2-0 LOGICLK_DIV_PRE R/W 4h Sets pre-divider value for logic clock divider. Output of the pre-divider
must be ≤ 3.2GHz. Values other than those listed below are
reserved.
  • 1h = /1
  • 2h = /2
  • 4h = /4

7.1.16 R15 Register (Offset = Fh) [Reset = 0002h]

R15 is shown in Table 7-18.

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Table 7-18 R15 Register Field Descriptions
Bit Field Type Reset Description
15-3 UNDISCLOSED R/W 0h Program this field to 0x0.
2-1 LOGICLK2_DIV R/W 1h Sets the divider value for LOGICLKOUT1 logic clock.
0 LOGICLK2_EN R/W 0h Enables the LOGICLKOUT1
  • 0h = LOGISYSREFOUT
  • 1h = LOGICLKOUT1

7.1.17 R16 Register (Offset = 10h) [Reset = 0030h]

R16 is shown in Table 7-19.

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Table 7-19 R16 Register Field Descriptions
Bit Field Type Reset Description
15-8 UNDISCLOSED R 0h Program this field to 0x0.
7-6 SYSREF_DLY_SCALE R/W 0h Sets the frequency range of the SYSREFOUT delay generator. Set according to phase interpolator frequency.
  • 0h = 400MHz to 800MHz
  • 1h = 200MHz to 400MHz
  • 2h = 150MHz to 200MHz
  • 3h = Reserved
5-4 SYSREFREQ_DLY_STEP R/W 3h Sets the step size of the delay element used in the SYSREFREQ path, both for SYSREFREQ input delay and for clock position captures. The recommended frequency range for each step size creates the maximum number of usable steps for a given CLKIN frequency. The ranges include some overlap to account for process and temperature variations. If the CLKIN frequency is covered by an overlapping span, larger delay step sizes improve the likelihood of detecting a CLKIN rising edge during a clock position capture. However, since larger values include more delay steps, larger step sizes have greater total delay variation across PVT relative to smaller step sizes.
  • 0h = 28ps (1.4GHz to 2.7GHz)
  • 1h = 15ps ( 2.4GHz to 4.7GHz)
  • 2h = 11ps (3.1GHz to 5.7GHz)
  • 3h = 8ps (4.5GHz to 12.8GHz)
3-2 SYSREFREQ_VCM_OFFSET R/W 0h Sets the voltage offset at SYSREFREQ P vs N
  • 0h = 25mV
  • 1h = 50mV
  • 2h = 100mV
  • 3h = 150mV
1-0 SYSREFREQ_VCM R/W 0h Sets the SYSREFREQ input pins common mode voltage
  • 0h = Zero offset (AC coupled)
  • 1h = Pin P biased higher than pin N (AC coupled)
  • 2h = Pin N higher than pin P (AC coupled)
  • 3h = No Bias (DC coupled)

7.1.18 R17 Register (Offset = 11h) [Reset = 0005h]

R17 is shown in Table 7-20.

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Table 7-20 R17 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R 0h Program this field to 0x0.
11-8 UNDISCLOSED R/W 0h Program this field to 0x0.
7-6 SYSREFREQ_INPUT R/W 0h Sets the functionality of the SYSREFREQ block
  • 0h = SYSREFREQ Pin
  • 1h = Force Low
  • 2h = Reserved
  • 3h = Force High
5 SYSWND_UPDATE_STOP R/W 0h Stops the windowing after setting bit to high.
4 SYNC_STOP R/W 0h Stops the reset generation after setting bit to high.
3 SYSWND_LATCH R/W 0h Sets the SYSREF Windowing at first rising edge of the SYNC input
2 SYSREFREQ_CLR R/W 1h Reset synchronization path timing for SYSREFREQ signal. Holding this bit high keeps internal SYSREFREQ signal low in all modes except SYSREF repeater mode, overriding the state of SYSREFREQ_INPUT[0]. This bit must be set and cleared once before the SYNC or clock position capture operations are performed.
1-0 SYSREFREQ_MODE R/W 1h Sets the SYSREFREQ input mode function
  • 0h = SYNC
  • 1h = SYSREFREQ
  • 2h = SYSREF Windowing
  • 3h = Reserved

7.1.19 R18 Register (Offset = 12h) [Reset = 0000h]

R18 is shown in Table 7-21.

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Table 7-21 R18 Register Field Descriptions
Bit Field Type Reset Description
15-6 UNDISCLOSED R 0h Program this field to 0x0.
5-0 SYSREFREQ_DLY R/W 0h Sets the delay line step for the external SYSREFREQ signal. Each delay line step delays the SYSREFREQ signal by an amount equal to SYSREFREQ_DLY x SYSREFREQ_DLY_STEP. In SYNC mode, the value for this field can be determined based on the rb_CLKPOS value to satisfy the internal setup and hold time of the SYNC signal with respect to the CLKIN signal. In SYSREF Repeater Mode, the value for this field can be used as a coarse global delay. Values greater than 0x3F are invalid. Since larger values include more delay steps, larger values have greater total step size variation across PVT relative to smaller values. Refer to the data sheet or the device TICS Pro profile for detailed description of the delay step computation procedure.

7.1.20 R19 Register (Offset = 13h) [Reset = 0004h]

R19 is shown in Table 7-22.

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Table 7-22 R19 Register Field Descriptions
Bit Field Type Reset Description
15-7 UNDISCLOSED R 0h Program this field to 0x0.
6 SYSREF_DLY_BYP R/W 0h Sets the SYSREF delay bypass
5-2 SYSREF_PULSE_CNT R/W 1h Programs the number of pulses generated in pulser mode. The pulser is a counter gating the SYSREF divider; consequently, the pulse duration and frequency are equal to the duty cycle and frequency of the SYSREF divider output, respectively.
  • 0h = Reserved
  • 1h = 1 pulse
  • 2h = 2 pulses
  • Fh = 15 pulses
1-0 SYSREF_MODE R/W 0h Controls how the SYSREF signal is generated and is also impacted by the SYSREF_DLY_BYP field. Continuous mode generates a continuous SYSREF clock that is derived from the SYSREF divider and delay. In pulser mode, a pulse at the SYSREFREQ pin causes a specific number (determined by SYSREF_PULSE_CNT) of pulses to be generated for the SYSREF outputs. In Repeater mode, a pulse at the SYSREFREQ pins generates a single pulse at the SYSREF outputs and only the propagation delay through the device is added.
  • 0h = Continuous
  • 1h = Pulser
  • 2h = Repeater
  • 3h = Repeater Retime

7.1.21 R20 Register (Offset = 14h) [Reset = 8082h]

R20 is shown in Table 7-23.

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Table 7-23 R20 Register Field Descriptions
Bit Field Type Reset Description
15-14 SYSREF_DLY_DIV R/W 2h Sets the delay generator clock division, determining fINTERPOLATOR and the delay generator resolution.
  • 0h = /2 (≤ 1.6GHz)
  • 1h = /4 (1.6GHz to 3.2GHz)
  • 2h = /8 (3.2GHz to 6.4GHz)
  • 4h = /16 (6.4GHz to 12.8GHz)
13-2 SYSREF_DIV R/W 20h Sets the SYSREF divider. Maximum input frequency from SYSREF_DIV_PRE must be ≤ 3200MHz. Maximum output frequency must be ≤ 100MHz. Odd divides (with duty cycle < 50%) are only allowed when the delay generators are bypassed.
  • 0h = Reserved
  • 1h = Reserved
  • 2h = /2
  • 3h = /3
  • FFFh = /4095
1-0 SYSREF_DIV_PRE R/W 2h Sets the SYSREF pre-divider. Maximum output frequency must be ≤ 3.2GHz.
  • 0h = /1
  • 1h = /2
  • 2h = /4
  • 3h = Reserved

7.1.22 R21 Register (Offset = 15h) [Reset = 01FCh]

R21 is shown in Table 7-24.

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Table 7-24 R21 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-2 SYSREF0_DLY R/W 7Fh Sets the delay step for the SYSREFOUT0 delay generator. In each quadrant, delay has 127 steps.
1-0 SYSREF0_DLY_PHASE R/W 0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT0 delay generator retimer.
  • 0h = ICLK'
  • 1h = QCLK'
  • 2h = ICLK
  • 3h = QCLK

7.1.23 R22 Register (Offset = 16h) [Reset = 01FCh]

R22 is shown in Table 7-25.

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Table 7-25 R22 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-2 SYSREF1_DLY R/W 7Fh Sets the delay step for the SYSREFOUT1 delay generator. In each quadrant, delay has 127 steps.
1-0 SYSREF1_DLY_PHASE R/W 0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT1 delay generator retimer.
  • 0h = ICLK'
  • 1h = QCLK'
  • 2h = QCLK
  • 3h = ICLK

7.1.24 R23 Register (Offset = 17h) [Reset = 01FCh]

R23 is shown in Table 7-26.

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Table 7-26 R23 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-2 SYSREF2_DLY R/W 7Fh Sets the delay step for the SYSREFOUT2 delay generator. In each quadrant, delay has 127 steps.
1-0 SYSREF2_DLY_PHASE R/W 0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT2 delay generator retimer.
  • 0h = ICLK'
  • 1h = QCLK'
  • 2h = QCLK
  • 3h = ICLK

7.1.25 R24 Register (Offset = 18h) [Reset = 01FCh]

R24 is shown in Table 7-27.

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Table 7-27 R24 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-2 SYSREF3_DLY R/W 7Fh Sets the delay step for the SYSREFOUT3 delay generator. In each quadrant, delay has 127 steps.
1-0 SYSREF3_DLY_PHASE R/W 0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT3 delay generator retimer.
  • 0h = ICLK'
  • 1h = QCLK'
  • 2h = QCLK
  • 3h = ICLK

7.1.26 R25 Register (Offset = 19h) [Reset = 01FCh]

R25 is shown in Table 7-28.

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Table 7-28 R25 Register Field Descriptions
Bit Field Type Reset Description
15-9 UNDISCLOSED R/W 0h Program this field to 0x0.
8-2 LOGISYSREF_DLY R/W 7Fh Sets the delay step for the LOGISYSREF delay generator. In each quadrant, delay has 127 steps.
1-0 LOGISYSREF_DLY_PHASE R/W 0h Sets the quadrature phase of the interpolator clock used for the LOGISYSREFOUT delay generator retimer.
  • 0h = ICLK'
  • 1h = QCLK'
  • 2h = QCLK
  • 3h = ICLK

7.1.27 R26 Register (Offset = 1Ah) [Reset = 00D1h]

R26 is shown in Table 7-29.

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Table 7-29 R26 Register Field Descriptions
Bit Field Type Reset Description
15-8 UNDISCLOSED R/W 0h Program this field to 0x0.
7-5 SMCLK_DIV R/W 6h Sets state machine clock divider. Further divides the output of the state machine clock pre-divider. Input frequency from SMCLK_DIV_PRE must be ≤ 1600MHz. Output frequency must be ≤ 30MHz. Divide value is 2SMCLK_DIV.
  • 0h = /1
  • 1h = /2
  • 2h = /4
  • 3h = /8
  • 4h = /16
  • 5h = /32
  • 6h = /64
  • 7h = /128
4-1 SMCLK_DIV_PRE R/W 8h Pre-divider for State Machine clock (one hot divider).The state machine clock is divided from the input clock. The output of the pre-divider must be ≤1600MHz. Values other than those listed are reserved.
  • 2h = /2
  • 4h = /4
  • 8h = /8
0 SMCLK_EN R/W 1h Enables the state machine clock generator. Only required to calibrate the multiplier, and for multiplier lock detect (including on MUXOUT pin). If the multiplier is not used, or if the multiplier lock detect feature is not used, the state machine clock generator can be disabled to minimize crosstalk.

7.1.28 R27 Register (Offset = 1Bh) [Reset = 3609h]

R27 is shown in Table 7-30.

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Table 7-30 R27 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 3h Program this field to 0x3.
11 MULT_HIPFD_EN R/W 0h Above 4.2GHz frequency in multiplier mode, to optimized the current, toggle this bit low to high along with R0. To set the bit high without R0, increase a current with 20mA.
10 UNDISCLOSED R/W 1h Program this field to 0x1.
9 FCAL_EN R/W 1h Enables Frequency calibration. Writing this register with this bit high triggers a multiplier frequency calibration. If the multiplier is unused, set to 0.
8-7 UNDISCLOSED R/W 0h Program this field to 0x0.
6 CLK_DIV_RST R/W 0h Resets the main clock divider. If the clock divider value is changed during operation, set this bit high then low after setting the new divider value. Synchronizing the device with the SYSREFREQ pins in SYSREFREQ_MODE = 0x0 and SYNC_EN = 0x1 also resets the main clock divider. This bit has no effect when outside of Divider Mode.
5-3 CLK_DIV R/W 1h CLK_DIV and CLK_MULT are aliases for the same field.
When CLK_MUX=1 (Buffer Mode), this field is ignored.
When CLK_MUX = 2 (Divider Mode), the clock divider is CLK_DIV + 1. Valid range for CLK_DIV is 1 to 7. Setting this to 0 disables the main clock divider and reverts to buffer mode.
When CLK_MUX = 3 (Multiplier Mode), CLK_MULT the multiplier vaue is CLK_MULT. Valid range is 1 to 7.
2-0 CLK_MUX R/W 1h Selects the function for the main clock outputs
  • 0h = Reserved
  • 1h = Buffer
  • 2h = Dividers
  • 3h = Multiplier

7.1.29 R29 Register (Offset = 1Dh) [Reset = 0000h]

R29 is shown in Table 7-31.

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Table 7-31 R29 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_CLKPOS[31:16] R 0h Stores a snapshot of the CLKIN signal rising edge positions relative to a SYSREFREQ rising edge, with the snapshot starting from the LSB and ending at the MSB. Each bit represents a sample of the CLKIN signal, separated by a delay determined by the SYSREFREQ_DLY_STEP field. The first and last bits of rb_CLKPOS are always set, indicating uncertainty at the capture window boundary conditions. CLKIN rising edges are represented by every sequence of two set bits from LSB to MSB, including bits at the boundary conditions. The position of the CLKIN rising edges in the snapshot, along with the CLKIN signal period and the delay step size, can be used to compute the value of SYSREFREQ_DLY_STEP which maximizes setup and hold times for SYNC signals on the SYSREFREQ pins.

7.1.30 R30 Register (Offset = 1Eh) [Reset = 0000h]

R30 is shown in Table 7-32.

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Table 7-32 R30 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_CLKPOS R 0h LSBs of rb_CLKPOS field.

7.1.31 R31 Register (Offset = 1Fh) [Reset = 0000h]

R31 is shown in Table 7-33.

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Table 7-33 R31 Register Field Descriptions
Bit Field Type Reset Description
15-14 UNDISCLOSED R 0h Program this field to 0x0.
13-11 UNDISCLOSED R 0h Program this field to 0x0.
10-0 rb_TEMPSENSE R 0h Readback value of on-die temperature sensor.

7.1.32 R32 Register (Offset = 20h) [Reset = 0000h]

R32 is shown in Table 7-34.

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Table 7-34 R32 Register Field Descriptions
Bit Field Type Reset Description
15-0 rb_VER_ID R 0h Version ID.

7.1.33 R36 Register (Offset = 24h) [Reset = 84A3h]

R36 is shown in Table 7-35.

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Table 7-35 R36 Register Field Descriptions
Bit Field Type Reset Description
15-10 UNDISCLOSED R/W 21h Program this field to 0x42.
9-8 UNDISCLOSED R/W 0h Program this field to 0x3.
7-6 UNDISCLOSED R/W 2h Program this field to 0x0.
5-0 UNDISCLOSED R/W 23h Program this field to 0x16.

7.1.34 R37 Register (Offset = 25h) [Reset = 0000h]

R37 is shown in Table 7-36.

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Table 7-36 R37 Register Field Descriptions
Bit Field Type Reset Description
15 UNDISCLOSED R 0h Program this field to 0x0.
14-1 UNDISCLOSED R 0h Program this field to 0x0.
0 rb_LOCK_DETECT R 0h Reads back the lock detect status in multiplier mode
  • 0h = Unlock
  • 1h = Lock Detect

7.1.35 R39 Register (Offset = 27h) [Reset = 78E1h]

R39 is shown in Table 7-37.

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Table 7-37 R39 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 4h Program this field to 0x4.
8-4 UNDISCLOSED R/W Eh Program this field to 0x16.
3-0 UNDISCLOSED R/W 1h Program this field to 0x1.

7.1.36 R40 Register (Offset = 28h) [Reset = 78E1h]

R40 is shown in Table 7-38.

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Table 7-38 R40 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 4h Program this field to 0x4.
8-4 UNDISCLOSED R/W Eh Program this field to 0x16.
3-0 UNDISCLOSED R/W 1h Program this field to 0x3.

7.1.37 R41 Register (Offset = 29h) [Reset = 78F3h]

R41 is shown in Table 7-39.

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Table 7-39 R41 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 4h Program this field to 0x2.
8-4 UNDISCLOSED R/W Fh Program this field to 0x14.
3-0 UNDISCLOSED R/W 3h Program this field to 0x1.

7.1.38 R42 Register (Offset = 2Ah) [Reset = 76F3h]

R42 is shown in Table 7-40.

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Table 7-40 R42 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 3h Program this field to 0x3.
8-4 UNDISCLOSED R/W Fh Program this field to 0x14.
3-0 UNDISCLOSED R/W 3h Program this field to 0x1.

7.1.39 R43 Register (Offset = 2Bh) [Reset = 7707h]

R43 is shown in Table 7-41.

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Table 7-41 R43 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 3h Program this field to 0x3.
8-4 UNDISCLOSED R/W 10h Program this field to 0x14.
3-0 UNDISCLOSED R/W 7h Program this field to 0x1.

7.1.40 R44 Register (Offset = 2Ch) [Reset = 7707h]

R44 is shown in Table 7-42.

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Table 7-42 R44 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 7h Program this field to 0x7.
11-9 UNDISCLOSED R/W 3h Program this field to 0x2.
8-4 UNDISCLOSED R/W 10h Program this field to 0x16.
3-0 UNDISCLOSED R/W 7h Program this field to 0x1.

7.1.41 R45 Register (Offset = 2Dh) [Reset = 2ABFh]

R45 is shown in Table 7-43.

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Table 7-43 R45 Register Field Descriptions
Bit Field Type Reset Description
15-12 UNDISCLOSED R/W 2h Program this field to 0x2.
11-10 UNDISCLOSED R/W 2h Program this field to 0x3.
9-8 UNDISCLOSED R/W 2h Program this field to 0x3.
7-6 UNDISCLOSED R/W 2h Program this field to 0x3.
5-4 UNDISCLOSED R/W 3h Program this field to 0x3.
3-2 UNDISCLOSED R/W 3h Program this field to 0x3.
1-0 UNDISCLOSED R/W 3h Program this field to 0x3.

7.1.42 R54 Register (Offset = 36h) [Reset = 0000h]

R54 is shown in Table 7-44.

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Table 7-44 R54 Register Field Descriptions
Bit Field Type Reset Description
15-14 UNDISCLOSED R 0h Program this field to 0x0.
13-4 UNDISCLOSED R/W 0h Program this field to 0x0.
3-2 UNDISCLOSED R/W 0h Program this field to 0x3.
1-0 UNDISCLOSED R/W 0h Program this field to 0x2.

7.1.43 R55 Register (Offset = 37h) [Reset = 0000h]

R55 is shown in Table 7-45.

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Table 7-45 R55 Register Field Descriptions
Bit Field Type Reset Description
15-6 UNDISCLOSED R/W 0h Program this field to 0x0.
5-0 DEV_IOPT_CTRL R/W 0h Set this field to 0x6 in all modes, also in powerdown.
Set this field to 0x6 before calibration in multiplier mode and changed to 0x1 after calibration

7.1.44 R77 Register (Offset = 4Dh) [Reset = 0000h]

R77 is shown in Table 7-46.

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Table 7-46 R77 Register Field Descriptions
Bit Field Type Reset Description
15-2 UNDISCLOSED R/W 0h Program this field to 0x0.
1-0 UNDISCLOSED R/W 0h Program this field to 0x2.