SNAS850 December   2024 LMX1205

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Input
        1. 6.3.3.1 Clock Input Adjustable Delay
      4. 6.3.4 Clock Outputs
        1. 6.3.4.1 Clock Output Buffers
        2. 6.3.4.2 Clock Output Adjustable Delay
        3. 6.3.4.3 Clock MUX
        4. 6.3.4.4 Clock Divider
        5. 6.3.4.5 Clock Multiplier
          1. 6.3.4.5.1 General Information About the Clock Multiplier
          2. 6.3.4.5.2 State Machine Clock for the Clock Multiplier
            1. 6.3.4.5.2.1 State Machine Clock
          3. 6.3.4.5.3 Calibration for the Clock Multiplier
          4. 6.3.4.5.4 Lock Detect for the Clock Multiplier
      5. 6.3.5 LOGICLK Outputs
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 LOGISYSREF Output Buffer
          3. 6.3.6.1.3 SYSREF Frequency and Delay Generation
          4. 6.3.6.1.4 SYSREFREQ Pins and SYSREFREQ SPI Controlled Fields
            1. 6.3.6.1.4.1 SYSREFREQ Pins Common-Mode Voltage
            2. 6.3.6.1.4.2 SYSREFREQ Windowing Feature
              1. 6.3.6.1.4.2.1 General Procedure Flowchart for SYSREF Windowing Operation
              2. 6.3.6.1.4.2.2 Other Guidance For SYSREF Windowing
              3. 6.3.6.1.4.2.3 For Glitch-Free Output
              4. 6.3.6.1.4.2.4 If Using SYNC Feature
              5. 6.3.6.1.4.2.5 SYNC Feature
      7. 6.3.7 Power-Up Timing
      8. 6.3.8 Treatment of Unused Pins
    4. 6.4 Device Functional Modes Configurations
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Reference
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
        3. 8.1.1.3 Application Plots
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7 Register Map

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWERDOWN RESET
R1 0 0 0 0 0 0 0 0 0 0 0 LD_DIS READBACK_CTRL 0 1 1
R2 0 0 0 0 0 0 TEMPSENSE_EN SYNC_EN 1 SYSREF_EN 1 LOGIC_EN CH3_EN CH2_EN CH1_EN CH0_EN
R3 0 0 0 0 0 0 0 0 0 CLKIN_DLY
R4 0 0 0 0 0 CLK0_DLY CLK0_PWR CLK0_EN
R5 0 0 0 0 0 CLK1_DLY CLK1_PWR CLK1_EN
R6 0 0 0 0 0 CLK2_DLY CLK2_PWR CLK2_EN
R7 0 0 0 0 0 CLK3_DLY CLK3_PWR CLK3_EN
R8 0 SYSREF0_PWR_LOW SYSREF0_AC 1 1 1 SYSREF0_VCM SYSREF0_PWR SYSREF0_EN
R9 0 SYSREF1_PWR_LOW SYSREF1_AC 1 1 1 SYSREF1_VCM SYSREF1_PWR SYSREF1_EN
R10 0 SYSREF2_PWR_LOW SYSREF2_AC 1 1 1 SYSREF2_VCM SYSREF2_PWR SYSREF2_EN
R11 0 SYSREF3_PWR_LOW SYSREF3_AC 1 1 1 SYSREF3_VCM SYSREF3_PWR SYSREF3_EN
R12 0 0 0 LOGICLK_FMT 0 0 LOGICLK_VCM LOGICLK_PWR LOGICLK_EN
R13 0 0 0 LOGISYSREF_FMT 0 0 LOGISYSREF_VCM LOGISYSREF_PWR LOGISYSREF_EN
R14 LOGICLK_DIV_RST 0 0 LOGICLK_DIV LOGICLK_DIV_PRE
R15 0 0 0 0 0 0 0 0 0 0 0 0 0 LOGICLK2_DIV LOGICLK2_EN
R16 0 0 0 0 0 0 0 0 SYSREF_DLY_SCALE SYSREFREQ_DLY_STEP SYSREFREQ_VCM_OFFSET SYSREFREQ_VCM
R17 0 0 0 0 0 0 0 0 SYSREFREQ_INPUT SYSWND_UPDATE_STOP SYNC_STOP SYSWND_LATCH SYSREFREQ_CLR SYSREFREQ_MODE
R18 0 0 0 0 0 0 0 0 0 0 SYSREFREQ_DLY
R19 0 0 0 0 0 0 0 0 0 SYSREF_DLY_BYP SYSREF_PULSE_CNT SYSREF_MODE
R20 SYSREF_DLY_DIV SYSREF_DIV SYSREF_DIV_PRE
R21 0 0 0 0 0 0 0 SYSREF0_DLY SYSREF0_DLY_PHASE
R22 0 0 0 0 0 0 0 SYSREF1_DLY SYSREF1_DLY_PHASE
R23 0 0 0 0 0 0 0 SYSREF2_DLY SYSREF2_DLY_PHASE
R24 0 0 0 0 0 0 0 SYSREF3_DLY SYSREF3_DLY_PHASE
R25 0 0 0 0 0 0 0 LOGISYSREF_DLY LOGISYSREF_DLY_PHASE
R26 0 0 0 0 0 0 0 0 SMCLK_DIV SMCLK_DIV_PRE SMCLK_EN
R27 0 1 1 0 MULT_HIPFD_EN 1 FCAL_EN 0 0 CLK_DIV_RST CLK_DIV CLK_MUX
R29 rb_CLKPOS[31:16]
R30 rb_CLKPOS[15:0]
R31 0 0 0 0 0 rb_TEMPSENSE
R32 rb_VER_ID
R36 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0
R37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rb_LOCK_DETECT
R39 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 1
R40 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1
R41 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1
R42 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1
R43 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1
R44 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 1
R45 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
R54 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
R55 0 0 0 0 0 0 0 0 0 0 DEV_IOPT_CTRL
R77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0