SNAS855F November   2023  – November 2025 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1112 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
          1. 8.3.4.2.1 Slew Rate Control through Pin
          2. 8.3.4.2.2 Slew Rate Control Through SMBus
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
        6. 8.3.4.6 Fail-Safe Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 and LMKDB1120FS Registers
    2. 9.2 LMKDB1112 Registers
    3. 9.3 LMKDB1108 and LMKDB1108FS Registers
    4. 9.4 LMKDB1104 and LMKDB1104FS Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

9.2 LMKDB1112 Registers

Table 9-29 lists the memory-mapped registers for the LMKDB1112 registers. All register offset addresses not listed in Table 9-29 should be considered as reserved locations and the register contents should not be modified.

Table 9-29 LMKDB1112 Registers
OffsetAcronymRegister NameSection
0hR0Output Enable Control for CLK0 through CLK5Section 9.2.1
1hR1Output Enable Control for CLK6 through CLK11Section 9.2.2
2hR2OE Pin Readback for CLK0 through CLK5Section 9.2.3
3hR3OE Pin Readback for CLK6 through CLK11Section 9.2.4
4hR4ACP Enable Control and SBI_EN ReadbackSection 9.2.5
5hR5Device InfoSection 9.2.6
6hR6Device Info (cont.)Section 9.2.7
7hR7SMBus Byte CounterSection 9.2.8
8hR8SBI Mask for CLK0 through CLK5Section 9.2.9
9hR9SBI Mask for CLK6 through CLK11Section 9.2.10
BhR11SBI Readback for CLK0 through CLK5Section 9.2.11
ChR12SBI Readback for CLK6 through CLK11Section 9.2.12
11hR17Output Amplitude ControlSection 9.2.13
12hR18Input Receiver Bias and Termination Resistor ControlSection 9.2.14
14hR20Output Slew Rate Select MSB for CLK0 through CLK5Section 9.2.15
15hR21Output Slew Rate Select MSB for CLK6 through CLK11Section 9.2.16
26hR38Non-clearable SMBus Write LockSection 9.2.17
27hR39LOS Status and Clearable SMBus Write LockSection 9.2.18
5BhR91Slew Rate Speed Options 1 and 2 AssignmentsSection 9.2.19
5ChR92Slew Rate Speed Options 3 and 4 AssignmentsSection 9.2.20
61hR97Slew Rate Mode SelectionSection 9.2.21
62hR98Output Slew Rate Select LSB for CLK0 through CLK5Section 9.2.22
63hR99Output Slew Rate Select LSB for CLK6 through CLK11Section 9.2.23

Complex bit access types are encoded to fit into small table cells. Table 9-30 shows the codes that are used for access types in this section.

Table 9-30 LMKDB1112 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WMCWWrite
WSCWWrite
Reset or Default Value
-nValue after reset or the default value

9.2.1 R0 Register (Offset = 0h) [Reset = B7h]

R0 is shown in Table 9-31.

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Table 9-31 R0 Register Field Descriptions
BitFieldTypeResetDescription
7CLK_EN_5R/W1h Output Enable for CLK5
0h = Output Disabled (low/low)
1h = Output Enabled
6RESERVEDR0h Reserved bits
5CLK_EN_4R/W1h Output Enable for CLK4
0h = Output Disabled (low/low)
1h = Output Enabled
4CLK_EN_3R/W1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
3RESERVEDR0h Reserved bits
2CLK_EN_2R/W1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
1CLK_EN_1R/W1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
0CLK_EN_0R/W1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled

9.2.2 R1 Register (Offset = 1h) [Reset = 6Fh]

R1 is shown in Table 9-32.

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Table 9-32 R1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved bits
6CLK_EN_11R/W1h Output Enable for CLK11
0h = Output Disabled (low/low)
1h = Output Enabled
5CLK_EN_10R/W1h Output Enable for CLK10
0h = Output Disabled (low/low)
1h = Output Enabled
4RESERVEDR0h Reserved bits
3CLK_EN_9R/W1h Output Enable for CLK9
0h = Output Disabled (low/low)
1h = Output Enabled
2CLK_EN_8R/W1h Output Enable for CLK8
0h = Output Disabled (low/low)
1h = Output Enabled
1CLK_EN_7R/W1h Output Enable for CLK7
0h = Output Disabled (low/low)
1h = Output Enabled
0CLK_EN_6R/W1h Output Enable for CLK6
0h = Output Disabled (low/low)
1h = Output Enabled

9.2.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 9-33.

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Table 9-33 R2 Register Field Descriptions
BitFieldTypeResetDescription
7RB_OEb_5R0h Status of OEb5
6RESERVEDR0h Reserved bits
5RB_OEb_4R0h Status of OEb4
4RB_OEb_3R0h Status of OEb3
3RESERVEDR0h Reserved bits
2RB_OEb_2R0h Status of OEb2
1RB_OEb_1R0h Status of OEb1
0RB_OEb_0R0h Status of OEb0

9.2.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-34.

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Table 9-34 R3 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved bits
6RB_OEb_11R0h Status of OEb11
5RB_OEb_10R0h Status of OEb10
4RESERVEDR0h Reserved bits
3RB_OEb_9R0h Status of OEb9
2RB_OEb_8R0h Status of OEb8
1RB_OEb_7R0h Status of OEb7
0RB_OEb_6R0h Status of OEb6

9.2.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-35.

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Table 9-35 R4 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved bits
4BANK1_ACP_ENABLER/W1h Enable Automatic Clock Parking to low/low when LOS event is detected, BANK1
3:1RESERVEDR0h Reserved bits
0RB_SBI_ENQR0h Status of SBI_ENQ

9.2.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-36.

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Table 9-36 R5 Register Field Descriptions
BitFieldTypeResetDescription
7:4REV_IDR0h Silicon revision
3:0VENDOR_IDRAh Vendor ID

9.2.7 R6 Register (Offset = 6h) [Reset = 50h]

R6 is shown in Table 9-37.

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Table 9-37 R6 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEV_IDR50h Device ID

9.2.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-38.

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Table 9-38 R7 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved bits
4:0SMBUS_BCR/W7h SMBUS Block Read Byte Count

9.2.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 9-39.

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Table 9-39 R8 Register Field Descriptions
BitFieldTypeResetDescription
7SBI_MASK_5R/W0h Mask off Side-Band Disable for CLK5
6RESERVEDR0h Reserved bits
5SBI_MASK_4R/W0h Mask off Side-Band Disable for CLK4
4SBI_MASK_3R/W0h Mask off Side-Band Disable for CLK3
3RESERVEDR0h Reserved bits
2SBI_MASK_2R/W0h Mask off Side-Band Disable for CLK2
1SBI_MASK_1R/W0h Mask off Side-Band Disable for CLK1
0SBI_MASK_0R/W0h Mask off Side-Band Disable for CLK0

9.2.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 9-40.

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Table 9-40 R9 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved bits
6SBI_MASK_11R/W0h Mask off Side-Band Disable for CLK11
5SBI_MASK_10R/W0h Mask off Side-Band Disable for CLK10
4RESERVEDR0h Reserved bits
3SBI_MASK_9R/W0h Mask off Side-Band Disable for CLK9
2SBI_MASK_8R/W0h Mask off Side-Band Disable for CLK8
1SBI_MASK_7R/W0h Mask off Side-Band Disable for CLK7
0SBI_MASK_6R/W0h Mask off Side-Band Disable for CLK6

9.2.11 R11 Register (Offset = Bh) [Reset = 00h]

R11 is shown in Table 9-41.

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Table 9-41 R11 Register Field Descriptions
BitFieldTypeResetDescription
7SBI_CLK_5R0h Readback of Side-Band Disable for CLK5
6RESERVEDR0h Reserved bits
5SBI_CLK_4R0h Readback of Side-Band Disable for CLK4
4SBI_CLK_3R0h Readback of Side-Band Disable for CLK3
3RESERVEDR0h Reserved bits
2SBI_CLK_2R0h Readback of Side-Band Disable for CLK2
1SBI_CLK_1R0h Readback of Side-Band Disable for CLK1
0SBI_CLK_0R0h Readback of Side-Band Disable for CLK0

9.2.12 R12 Register (Offset = Ch) [Reset = 00h]

R12 is shown in Table 9-42.

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Table 9-42 R12 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved bits
6SBI_CLK_11R0h Readback of Side-Band Disable for CLK11
5SBI_CLK_10R0h Readback of Side-Band Disable for CLK10
4RESERVEDR0h Reserved bits
3SBI_CLK_9R0h Readback of Side-Band Disable for CLK9
2SBI_CLK_8R0h Readback of Side-Band Disable for CLK8
1SBI_CLK_7R0h Readback of Side-Band Disable for CLK7
0SBI_CLK_6R0h Readback of Side-Band Disable for CLK6

9.2.13 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 9-43.

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Table 9-43 R17 Register Field Descriptions
BitFieldTypeResetDescription
7:4AMPR/W6h Global Differential output Control = 0.6V to approximately 1V
25mV/step Default = 0.75V
0h = 600mV
1h = 625mV
2h = 650mV
3h = 675mV
4h = 700mV
5h = 725mV
6h = 750mV
7h = 775mV
8h = 800mV
9h = 825mV
Ah = 850mV
Bh = 875mV
Ch = 900mV
Dh = 925mV
Eh = 950mV
Fh = 975mV
3:0RESERVEDR0h Reserved bits

9.2.14 R18 Register (Offset = 12h) [Reset = 08h]

R18 is shown in Table 9-44.

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Table 9-44 R18 Register Field Descriptions
BitFieldTypeResetDescription
7d_RX_EN_AC_INPUTR/W0h Enable receiver bias when CLKIN is AC coupled
0h = DC coupled input
1h = AC coupled input
6d_RX_EN_RTERM_LSBR/W0h Enable termination resistors on CLKIN
0h = Input Termination R is disabled
1h = Input Termination R is enabled
5:4RESERVEDR0h Reserved bits
3PD_RESTOREBR/W1h Save Configuration in Power Down
0h = Config Cleared
1h = Config Saved
2:1RESERVEDR0h Reserved bits
0LOSb_RBR0h Real time read back of loss detect block output
0h = LOS event detected
1h = NO LOS event detected

9.2.15 R20 Register (Offset = 14h) [Reset = B7h]

R20 is shown in Table 9-45.

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Table 9-45 R20 Register Field Descriptions
BitFieldTypeResetDescription
7SLEWRATE_SEL_CLK5__MSBR/W1h MSB CLK5 slew rate select
6RESERVEDR0h Reserved bits
5SLEWRATE_SEL_CLK4__MSBR/W1h MSB CLK4 slew rate select
4SLEWRATE_SEL_CLK3__MSBR/W1h MSB CLK3 slew rate select
3RESERVEDR0h Reserved bits
2SLEWRATE_SEL_CLK2__MSBR/W1h MSB CLK2 slew rate select
1SLEWRATE_SEL_CLK1__MSBR/W1h MSB CLK1 slew rate select
0SLEWRATE_SEL_CLK0__MSBR/W1h MSB CLK0 slew rate select

9.2.16 R21 Register (Offset = 15h) [Reset = 6Fh]

R21 is shown in Table 9-46.

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Table 9-46 R21 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved bits
6SLEWRATE_SEL_CLK11__MSBR/W1h MSB CLK11 slew rate select
5SLEWRATE_SEL_CLK10__MSBR/W1h MSB CLK10 slew rate select
4RESERVEDR0h Reserved bits
3SLEWRATE_SEL_CLK9__MSBR/W1h MSB CLK9 slew rate select
2SLEWRATE_SEL_CLK8__MSBR/W1h MSB CLK8 slew rate select
1SLEWRATE_SEL_CLK7__MSBR/W1h MSB CLK7 slew rate select
0SLEWRATE_SEL_CLK6__MSBR/W1h MSB CLK6 slew rate select

9.2.17 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-47.

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Table 9-47 R38 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved bits
0WRITE_LOCKR/WMC0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control Risters cannot be written to. This bit can only be cleared by recycling power
0h = SMBus not locked for writing by this bit. See WRITE_LOCK_RW1C bit.
1h = SMBus locked for writing

9.2.18 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-48.

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Table 9-48 R39 Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0h Reserved
1LOS_EVTR/WSC0h LOS Event Status When high, indicates that a LOS event was detected. Can be cleared by writing a 1 to it.
0h = No LOS event detected
1h = LOS event detected
0WRITE_LOCK_RW1CR/W0h Clearable SMBus Write Lock bit. When written to one, the SMBus control Risters cannot be written to. This bit can be cleared by writing a 1 to it.
0h = SMBus not locked for writing by this bit. See WRITE_LOCK bit.
1h = SMBus locked for writing

9.2.19 R91 Register (Offset = 5Bh) [Reset = 60h]

R91 is shown in Table 9-49.

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Table 9-49 R91 Register Field Descriptions
BitFieldTypeResetDescription
7:4SLEWRATE_OPT_2R/W6h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6 (Default for LMKDB1112)
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0SLEWRATE_OPT_1R/W0h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.2.20 R92 Register (Offset = 5Ch) [Reset = FAh]

R92 is shown in Table 9-50.

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Table 9-50 R92 Register Field Descriptions
BitFieldTypeResetDescription
7:4SLEWRATE_OPT_4R/WFh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0SLEWRATE_OPT_3R/WAh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.2.21 R97 Register (Offset = 61h) [Reset = 12h]

R97 is shown in Table 9-51.

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Table 9-51 R97 Register Field Descriptions
BitFieldTypeResetDescription
7SLEWRATE_CTRL_MOD_ER/W0h Sets which mode is used to change the outputs slew rates
0h = Pin mode
1h = SMBus mode
6RESERVEDR0h Reserved
5:3RESERVEDR0h Reserved
2:0RESERVEDR0h Reserved

9.2.22 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-52.

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Table 9-52 R98 Register Field Descriptions
BitFieldTypeResetDescription
7SLEWRATE_SEL_CLK5__LSBR/W0h LSB CLK5 Slew Rate Control
6RESERVEDR0h Reserved
5SLEWRATE_SEL_CLK4__LSBR/W0h LSB CLK4 Slew Rate Control
4SLEWRATE_SEL_CLK3__LSBR/W0h LSB CLK3 Slew Rate Control
3RESERVEDR0h Reserved
2SLEWRATE_SEL_CLK2__LSBR/W0h LSB CLK2 Slew Rate Control
1SLEWRATE_SEL_CLK1__LSBR/W0h LSB CLK1 Slew Rate Control
0SLEWRATE_SEL_CLK0__LSBR/W0h LSB CLK0 Slew Rate Control

9.2.23 R99 Register (Offset = 63h) [Reset = 00h]

R99 is shown in Table 9-53.

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Table 9-53 R99 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6SLEWRATE_SEL_CLK11__LSBR/W0h LSB CLK11 Slew Rate Control
5SLEWRATE_SEL_CLK10__LSBR/W0h LSB CLK10 Slew Rate Control
4RESERVEDR0h Reserved
3SLEWRATE_SEL_CLK9__LSBR/W0h LSB CLK9 Slew Rate Control
2SLEWRATE_SEL_CLK8__LSBR/W0h LSB CLK8 Slew Rate Control
1SLEWRATE_SEL_CLK7__LSBR/W0h LSB CLK7 Slew Rate Control
0SLEWRATE_SEL_CLK6__LSBR/W0h LSB CLK6 Slew Rate Control