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LMKDB1104

ACTIVE

4-output LP-HCSL clock buffer for PCIe PCIe Gen 1 to Gen 7

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Data sheet

LMKDB1104

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 3.3 Output supply voltage (V) 1.8, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
Number of outputs 4 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 3.3 Output supply voltage (V) 1.8, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
VQFN (REX) 28 16 mm² 4 x 4
  • LP-HCSL clock buffer and clock MUX that support:
    • PCIe Gen 1 to Gen 7
    • CC (Common Clock) and IR (Independent Reference) PCIe architectures
    • Input clock with or without SSC
  • Intel DB2000QL and DB1206 compliant:
    • All devices meet DB2000QL specifications
    • LMKDB1120 is pin-compatible to DB2000QL
    • LMKDB1112 is pin-compatible to DB1206
  • Extremely low additive jitter:
    • 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
    • 13fs maximum additive jitter for PCIe Gen 4
    • 5fs maximum additive jitter for PCIe Gen 5
    • 3fs maximum additive jitter for PCIe Gen 6
    • 2.1fs maximum additive jitter for PCIe Gen 7
  • Fail-safe input
  • Fail-safe outputs (LMKDB1120FS, LMKDB1108FS and LMKDB1104FS only)
  • Flexible power-up sequence
  • Automatic output disable
  • Individual output enable
  • SBI (Side Band Interface) for high-speed output enable or disable
  • LOS (Loss of Signal) input detection
  • 85Ω or 100Ω output impedance
  • 1.8V / 3.3V ± 10% power supply
  • –40°C to 105°C ambient temperature
  • LP-HCSL clock buffer and clock MUX that support:
    • PCIe Gen 1 to Gen 7
    • CC (Common Clock) and IR (Independent Reference) PCIe architectures
    • Input clock with or without SSC
  • Intel DB2000QL and DB1206 compliant:
    • All devices meet DB2000QL specifications
    • LMKDB1120 is pin-compatible to DB2000QL
    • LMKDB1112 is pin-compatible to DB1206
  • Extremely low additive jitter:
    • 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
    • 13fs maximum additive jitter for PCIe Gen 4
    • 5fs maximum additive jitter for PCIe Gen 5
    • 3fs maximum additive jitter for PCIe Gen 6
    • 2.1fs maximum additive jitter for PCIe Gen 7
  • Fail-safe input
  • Fail-safe outputs (LMKDB1120FS, LMKDB1108FS and LMKDB1104FS only)
  • Flexible power-up sequence
  • Automatic output disable
  • Individual output enable
  • SBI (Side Band Interface) for high-speed output enable or disable
  • LOS (Loss of Signal) input detection
  • 85Ω or 100Ω output impedance
  • 1.8V / 3.3V ± 10% power supply
  • –40°C to 105°C ambient temperature

The LMKDB devices are a family of extremely-low-jitter LP-HCSL buffers that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, fail-safe outputs, individual output active and inactive pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V supply voltages are supported. For LMKDB1120, 1.8V power supply saves 250mW power compared to 3.3V.

The LMKDB devices are a family of extremely-low-jitter LP-HCSL buffers that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, fail-safe outputs, individual output active and inactive pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V supply voltages are supported. For LMKDB1120, 1.8V power supply saves 250mW power compared to 3.3V.
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* Data sheet LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family datasheet (Rev. F) PDF | HTML 13 Nov 2025
Application brief Mitigating FLEXIO Use Case Risks as Clock Pins Using LMKDB11xxFS Fail-safe Output Clock Buffers PDF | HTML 26 Sep 2025
User guide RC19XXX, 9QXL2001X vs. LMKDB1XXX, CDCDB2000 Drop-In Replacement Guide. PDF | HTML 18 Jul 2024
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
White paper The Importance of Clocks in Data Centers PDF | HTML 21 Nov 2023

Design & development

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Evaluation board

LMKDB1104EVM — LMKDB1104 evaluation module

The LMKDB1104 Evaluation Module (EVM) is designed to provide a quick setup to evaluate the LMKDB1104 LP-HCSL buffer that supports PCIe Gen 1 to Gen 6 and is DB2000QL compliant. The printed circuit board (PCB) contains several jumpers and a USB connection to enable the LMKDB1104 with desired user (...)

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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMKDB1XXX IBIS Model

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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