SNAS894B July   2025  – December 2025 LMR60460-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Undervoltage Lockout (UVLO)
      2. 7.3.2 Soft Start and Recovery from Dropout
      3. 7.3.3 Frequency Selection With RT
      4. 7.3.4 MODE/SYNC Pin Control
      5. 7.3.5 Output Voltage Selection
      6. 7.3.6 Current Limit
      7. 7.3.7 Hiccup Mode
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Spread Spectrum
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Auto Mode Operation
        2. 7.4.2.2 Continuous Conduction Mode (CCM)
        3. 7.4.2.3 FPWM Operation
        4. 7.4.2.4 Minimum On-Time
        5. 7.4.2.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency Selection
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor (CBOOT) Selection
        6. 8.2.2.6 FB Voltage Divider for Adjustable Output Voltages
          1. 8.2.2.6.1 Feedforward Capacitor (CFF) Selection
        7. 8.2.2.7 RPG - PG Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Plane Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

7.4.2.3 FPWM Operation

In forced pulse width modulation (FPWM) mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See Section 6.5.

LMR60460-Q1 FPWM Mode Operation Figure 7-10 FPWM Mode Operation

FPWM mode can be achieved in any of the following ways:

  • Connect MODE/SYNC directly to RT pin
  • Apply an external voltage across MODE/SYNC and GND that is greater than VIH(MODE/SYNC)
  • Apply an appropriate external clock signal (see MODE/SYNC Pin Control)

Under operating conditions where the minimum on-time or minimum off-time can be exceeded, the frequency reduces even while operating in FPWM to maintain minimum timing specifications.