SNLA293 May   2022 DP83TC811R-Q1 , DP83TC811S-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Configuration
    1. 2.1 Schematic
  4. 3Software Configuration
  5. 4Testing PMA
    1. 4.1 PMA Testing Procedure
  6. 5Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  7. 6Testing SQI
    1. 6.1 SQI Testing Procedure
    2. 6.2 SQI Mapping with Link Quality
  8. 7Testing TDR
    1. 7.1 TDR Testing Procedure
  9. 8Testing EMC/EMI
  10. 9Revision History

4.1 PMA Testing Procedure

Note:
  • Before programming any of the test modes, DP83TC811 should be loaded with the respective initialization register configuration (master or slave) as described in earlier sections.
  • SLAVE transmit jitter requires link to be established between DUT and link-partner, hence register [0x0001] should read as 0x0065 before running the test.
Table 4-1 Programming PMA Test Modes
Test Mode Parameter Under Test MMD Register Value
Test Mode 1 Transmit Droop 0x01 0x0904 0x2001
Test Mode 2 MASTER transmit jitter 0x01 0x0904 0x4001
Test Mode 4 Transmit Distortion 0x01 0x0904 0x8001
0x1F 0x0462 0x0011
Test Mode 5 Transmit PSD 0x01 0x0904 0xA001
- SLAVE transmit jitter 0x1F 0x0462 0x0011

TX_TCLK (66.66MHz) is needed for Trasnmit Distortion and SLAVE transmit jitter testing. The clock is programmed to be transmitted on LED_0 using the write reg<0x0462> = 0x0011.