SNLA338A January   2020  – August 2022 DP83826E

 

  1.   KSZ8081MNX/RNB to DP83826 System Rollover
  2.   Trademarks
  3. 1Purpose
  4. 2Required Changes
    1. 2.1 Strap Resistor Value
    2. 2.2 External Capacitor on Pin 2
    3. 2.3 Duplex Strap on Pin 16 (DP83826 Basic Mode)
    4. 2.4 Selecting 10M with Auto-Negotiation Enabled (DP83826 Basic Mode)
    5. 2.5 Configuring LED_1 for Tx and Rx Activity for EtherCAT Slave (DP83826 Basic Mode)
    6. 2.6 Thermal Pad Adjustments in Layout
    7. 2.7 Physical Layer ID Register
  5. 3Potential Changes
    1. 3.1 MDIO Pull-Up Resistor on Pin 11
    2. 3.2 MDIO Register Writes
    3. 3.3 Capacitors on Center Tap of Magnetics
  6. 4Informational Changes
  7. 5Pinout Mapping
    1. 5.1 Pin Mapping
  8. 6DP83826 Strap Configurations
    1. 6.1 Bootstrap Configurations
  9. 7Revision History

5.1 Pin Mapping

The table below shows the pinout mapping between the DP83826 and KSZ8081MNX/RNB. For more details on the pin mapping as well as any updates made, please refer to the DP83826 Data sheet.

Table 5-1 Pinout Mapping
Pin No. KSZ8081MNX/RNB Pin Functions DP83826 BASIC Mode Pin Functions DP83826 ENHANCED Mode Pin Functions
1 GND Mode Select Mode Select
2 VDD_1.2 CEXT CEXT
3 VDDA_3.3 VDDA3V3 VDDA3V3
4 RXM RD_M RD_M
5 RXP RD_P RD_P
6 TXM TD_M TD_M
7 TXP TD_P TD_P
8 XO XO XO
9 XI XI/50MHzIn XI/50MHzIn
10 REXT RBIAS RBIAS
11 MDIO MDIO MDIO
12 MDC MDC MDC
13 PHYAD0 (RXD3) RX_D3 RX_D3
14 PHYAD1 (RXD2) RX_D2 RX_D2
15 RXD1/ PHYAD2 RX_D1 RX_D1
16 RXD0/ DUPLEX RX_D0 RX_D0
17 VDDIO VDDIO VDDIO
18 RXDV/ CONFIG2 RX_DV/CRS _DV RX_DV/CRS _DV
19 RXC/ B-CAST_OFF RX_CLK/50 MHz_Output RX_CLK/50 MHz_RMII
20 RXER/ ISO RX_ER RX_ER
21 INTRP/ NAND_Tree# INT PWRDN/INT
22 TXC TX_CLK TX_CLK
23 TXEN TX_EN TX_EN
24 TXD0 TX_D0 TX_D0
25 TXD1 TX_D1 TX_D1
26 TXD2 TX_D2 TX_D2
27 TXD3 TX_D3 TX_D3
28 COL/ CONFIG0 COL COL/LED2/GPIO
29 CRS/ CONFIG1 CRS CRS/LED3
30 LED0/ NWAYEN I LED0 LED0
31 LED1/ SPEED LED1 LED1
32 RST# RST_N RST_N