SNLA425A february   2023  – june 2023 DS160PR1601 , DS320PR1601

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Typical PCIe x16 Lane to DS160PR1601 and DS320PR1601 Channel Mapping
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

2.2 Channel Registers

The DS160PR1601 and DS320PR1601 feature two banks of channels for sides A and B, Bank 0 (Channels 0-3) and Bank 1 (Channels 4-7), each featuring a separate register set and requiring a unique SMBus secondary address.

Table 2-4 Channel Register Base Address Mapping
Channel Registers Base Address Channel Bank 0 Access Channel Bank 1 Access
0x00 Channel 0 registers Channel 4 registers
0x20 Channel 1 registers Channel 5 registers
0x40 Channel 2 registers Channel 6 registers
0x60 Channel 3 registers Channel 7 registers
0x80 Broadcast write channel bank 0 registers, read channel 0 registers Broadcast write channel bank 1 registers, read channel 4 registers
0xA0 Broadcast write channel 0-1 registers, read channel 0 registers Broadcast write channel 4-5 registers, read channel 4 registers
0xC0 Broadcast write channel 2-3 registers, read channel 2 registers Broadcast write channel 6-7 registers, read channel 6 registers
0xE0 Bank 0 Share registers Bank 1 Share registers
Table 2-5 RX Detect Status Register (Channel register base + Offset = 0x00) [reset = 0x0]
Bit Field Type Reset Description
7 rx_det_comp_p R 0x0 Rx Detect Positive Polarity Status: 0: Not detected 1: Detected - the value is latched.
6 rx_det_comp_n R 0x0 Rx Detect Negative Polarity Status: 0: Not detected 1: Detected - the value is latched.
5 RESERVED R 0x0 Reserved
4 RESERVED R 0x0 Reserved
3 RESERVED R 0x0 Reserved
2 RESERVED R 0x0 Reserved
1 RESERVED R 0x0 Reserved
0 RESERVED R 0x0 Reserved
Table 2-6 EQ Control Register (Channel register base + Offset = 0x01) [reset = 0x0]
Bit Field Type Reset Description
7 eq_stage1_bypass R/W 0x0 Enable EQ Stage 1 Bypass:
0: Bypass disabled
1: Bypass enabled
6 eq_stage11_3 R/W

0x0

 EQ Boost Stage 1 Control.
For details, see the device-specific data sheet.
5 eq_stage1_2 R/W 0x0
4 eq_stage1_1 R/W 0x0
3 eq_stage1_0 R/W 0x0
2 eq_stage2_2 R/W 0x0 EQ Boost Stage 2 Control.
For details, see the device-specific data sheet.
1 eq_stage2_1 R/W 0x0
0 eq_stage2_0 R/W 0x0
Table 2-7 Mute EQ Control Register (Channel register base + Offset = 0x02) [reset = 0x0]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 RESERVED R/W 0x0 Reserved
5 RESERVED R/W 0x0 Reserved
4 RESERVED R/W 0x0 Reserved
3 mute_eq R/W 0x0 Mute EQ output
2 RESERVED R 0x1 Reserved
1 RESERVED R 0x0 Reserved
0 RESERVED R 0x1 Reserved
Table 2-8 EQ Gain / Flat Gain Control Register (Channel register base + Offset = 0x03) [reset = 0x5]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 eq_profile_3 R/W 0x0 EQ mid-frequency boost profile
For details, see the device-specific data sheet.
5 eq_profile_2 R/W 0x0
4 eq_profile_1 R/W 0x0
3 eq_profile_0 R/W 0x0
2 Flat_gain_2 R/W 0x1 Flat Gain Select. For details, see the device-specific data sheet.
1 Flat_gain_1 R/W 0x0
0 Flat_gain_0 R/W 0x1
Table 2-9 RX Detect Control Register (Channel register base + Offset = 0x04) [reset = 0x0]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 RESERVED R 0x0 Reserved
5 RESERVED R 0x0 Reserved
4 RESERVED R 0x0 Reserved
3 RESERVED R 0x0 Reserved
2 mr_rx_det_man R/W 0x0 Manual override of rx_detect_p/n decision:
0: Rx Detect state machine is enabled
1: Rx Detect state machine is overridden – always valid Rx termination detected
1 en_rx_det_count R/W 0x0 Enable additional RX detect polling:
0: Additional Rx Detect Polling disabled
1: Additional Rx detect Polling enabled
0 sel_rx_det_count R/W 0x0 Select number of Valid Rx detect polls - gated by en_rx_det_count = 1. 0: 2x consecutive valid detections
1: 3x consecutive valid detections
Table 2-10 PD Override Register (Channel register base + Offset = 0x05) [reset = 0x3F]
Bit Field Type Reset Description
7 Device_en_override R/W 0x0 Enable power down overrides through SMBus/I2C
0: Manual override disabled
1: Manual override enabled
6:0 Device_en R/W 0x111111 Manual power down of redriver various blocks – gated by device_en_override = 1
000000: All blocks are disabled
111111: All blocks are enabled
Table 2-11 Bias Register (Channel register base + Offset = 0x06) [reset = 0x20]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 RESERVED R 0x0 Reserved
5 bias_current_2 R/W 0x1 Control bias current
4 bias_current_1 R/W 0x0 See MSB.
3 bias_current_0 R/W 0x0 See MSB.
2 RESERVED R 0x0 Reserved
1 RESERVED R 0x0 Reserved
0 RESERVED R 0x0 Reserved