SNLA425A february   2023  – june 2023 DS160PR1601 , DS320PR1601

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Typical PCIe x16 Lane to DS160PR1601 and DS320PR1601 Channel Mapping
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

2.1 Share Registers

Table 2-1 General Register (Offset = 0xE2) [reset = 0x0]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 rst_i2c_regs R/W/SC 0x0 Device Reset Control: Reset all I2C registers to default values (self- clearing).
5 RESERVED R 0x0 Reserved
4 RESERVED R 0x0 Reserved
3 RESERVED R 0x0 Reserved
2 RESERVED R 0x0 Reserved
1 RESERVED R 0x0 Reserved
0 frc_eeprm_rd R/W/SC 0x0 Override MODE and READ_EN_N status to force manual EEPROM Configuration Load.
Table 2-2 DEVICE_ID0 Register (Offset = 0xF0) [reset = 0x06]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 RESERVED R 0x0 Reserved
5 RESERVED R 0x0 Reserved
4 RESERVED R 0x0 Reserved
3 device_id0_3 R 0x0 Device ID0 [3:1]: 011
2 device_id0_2 R 0x1 see MSB
1 device_id0_1 R 0x1 see MSB
0 RESERVED R X Reserved
Table 2-3 DEVICE_ID1 Register (Offset = 0xF1) [reset = 0x28]
Bit Field Type Reset Description
7 device_id[7] R 0x0 Device ID 0010 1000: DS160PR1601, DS320PR1601
6 device_id[6] R 0x0 see MSB
5 device_id[5] R 0x1 see MSB
4 device_id[4] R 0x0 see MSB
3 device_id[3] R 0x1 see MSB
2 device_id[2] R 0x0 see MSB
1 device_id[1] R 0x0 see MSB
0 device_id[0] R 0x0 see MSB