SNLA499 October   2026 DS90UB926Q-Q1 , DS90UB927Q-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Regarding Design for Low-Resolution / Low-Frame-Rate Displays
    1. 2.1 How to Calculate Pixel Clock
    2. 2.2 How to Design Low-Resolution Displays Using DS90UB926-Q1 and DS90UB927-Q1
      1. 2.2.1 Pin Control or Register Override
  6. 3Debug Guide
    1. 3.1 Correct Configuration of Low Frequency Mode [LF Mode]
    2. 3.2 I2C Communication
      1. 3.2.1 I2C Fundamental Frequency Modification
      2. 3.2.2 I2C Watchdog Mechanism
      3. 3.2.3 DS90UB927Q-Q1 Auto-ACK Mechanism
    3. 3.3 Signal Integrity Testing
  7. 4Reference Documents

3.1 Correct Configuration of Low Frequency Mode [LF Mode]

When an I2C access timeout occurs from the SoC to the remote 926 or downstream devices; because the occurrence path is on the BCC, it is easily misjudged as I2C frequency interference, BCC watchdog, or cable signal integrity issues.

However, if the LF Mode is not correctly matched on both sides, the devices will operate under conditions that do not meet the specified range of the current Frequency Mode, which may manifest as LOCK, BCC, or Remote I2C anomalies.

10MHz PCLK 🡪 Both ends remain in high-frequency mode 🡪 Link is not within the guaranteed range 🡪 LOCK / BCC boundary is unstable
BCC packet reliability decreases → Remote I2C access anomaly → Software sees I2C timeout / intermittent fail

Debug Flowchart:
1. Measure actual PCLK (min / typ / max) Measure PCLK frequency using an oscilloscope
PCLK < 15MHz?

Yes: Enter Low-Frequency Mode check

No: Debug according to conventional link
2. Check 927 LFMODE strap or 0x04[1:0]; 10MHz target is 11b
3. Check 926 MODE_SEL / 0x02[1:0]; read 0x23[3] to confirm status