SNLA499 October   2026 DS90UB926Q-Q1 , DS90UB927Q-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Regarding Design for Low-Resolution / Low-Frame-Rate Displays
    1. 2.1 How to Calculate Pixel Clock
    2. 2.2 How to Design Low-Resolution Displays Using DS90UB926-Q1 and DS90UB927-Q1
      1. 2.2.1 Pin Control or Register Override
  6. 3Debug Guide
    1. 3.1 Correct Configuration of Low Frequency Mode [LF Mode]
    2. 3.2 I2C Communication
      1. 3.2.1 I2C Fundamental Frequency Modification
      2. 3.2.2 I2C Watchdog Mechanism
      3. 3.2.3 DS90UB927Q-Q1 Auto-ACK Mechanism
    3. 3.3 Signal Integrity Testing
  7. 4Reference Documents

1 Introduction

The PCLK range supported by FPD-Link DS90UB926Q-Q1 and DS90UB927Q-Q1 is 5MHz ≤ PCLK < 15MHz (LFMODE = 1) and 15MHz ≤ PCLK ≤ 85MHz (LFMODE = 0). This corresponds to application payload rates from 155Mbps to 2.635Gbps, and actual forward line rates from 525Mbps to 2.975Gbps. The forward link adopts NRZ encoding, and the Nyquist frequency is half of the line rate, which is 262.5MHz to 1.4875GHz.

For animated displays such as automotive headlights and ground projections, SoC data can be serialized and deserialized and successfully transmitted via DS90UB926Q-Q1 and DS90UB927Q-Q1 devices.

Figure 1-1 Design Path
SoC / GPU → DS90UB927Q-Q1 → FPD-Link III → DS90UB926Q-Q1 → TCON / Display
Table 1-1 Design Requirements under Different Resolutions
PCLK Range DS90UB927Q-Q1 DS90UB926Q-Q1 Design Conclusion
5MHz ≤ PCLK < 15MHz LFMODE = 1 LFMODE = High Must use Low-Frequency Mode
15MHz ≤ PCLK ≤ 85MHz LFMODE = 0 LFMODE = Low Use default high-frequency configuration