SNLA499 October   2026 DS90UB926Q-Q1 , DS90UB927Q-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Regarding Design for Low-Resolution / Low-Frame-Rate Displays
    1. 2.1 How to Calculate Pixel Clock
    2. 2.2 How to Design Low-Resolution Displays Using DS90UB926-Q1 and DS90UB927-Q1
      1. 2.2.1 Pin Control or Register Override
  6. 3Debug Guide
    1. 3.1 Correct Configuration of Low Frequency Mode [LF Mode]
    2. 3.2 I2C Communication
      1. 3.2.1 I2C Fundamental Frequency Modification
      2. 3.2.2 I2C Watchdog Mechanism
      3. 3.2.3 DS90UB927Q-Q1 Auto-ACK Mechanism
    3. 3.3 Signal Integrity Testing
  7. 4Reference Documents

2.2.1 Pin Control or Register Override

Table 2-1 DS90UB927Q-Q1 Design Specification
Configuration Method 5-15MHz Recommended Settings Description
Hardware Strap LFMODE pin pulled up to logic power supply with 10kΩ LFMODE=1; TI explicitly requires using a 10kΩ pull-up when set high.
Software Override Reg 0x04[1:0] = 11b bit1 selects register control, bit0 selects Low-Frequency Mode; for example, 0x80 becomes 0x83.
Table 2-2 DS90UB926Q-Q1 Design Specification
Configuration Method 5-15MHz Recommended Settings Description
Hardware Strap MODE_SEL selects Mode #5: R3=226kΩ, R4=102kΩ (1%) Corresponds to LFMODE High, i.e., 5MHz to <15MHz; not a standalone 10kΩ pull-up.
Software Override Reg 0x02[1:0] = 11b

bit1 enables register override, bit0 selects LFMODE;

Read back Reg 0x23[3]=1 to confirm actual status.

MODE_SEL is an analog configuration input, and the voltage divider target for Mode #5 is approximately 0.311 of VDD33. For hardware design, please refer to the DS90UB926Q-Q1 Pin Functions table and the actual package pinout: MODE_SEL is pin 15; the two voltage divider resistors at this node should be checked rather than simply adding a pull-up.

Software override is only applicable for bench verification with an accessible configuration path. The datasheet specifies that a PDB reset is required after LFMODE changes; meanwhile, PDB power-down will reset the control registers. 927 can be configured by the local SoC I2C; if 926 can only be accessed via BCC, an available BCC must exist first, or a local I2C master must be used on the deserializer side. If BCC is completely unavailable under the default strap and software cannot write to 926 0x02 from the SoC side, the hardware strap should be modified first in this case.