SNLS799 November   2025 DP83TC816-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device Comparison Table
  6. 5Device and Documentation Support
    1. 5.1 Device Support
      1. 5.1.1 Third-Party Products Disclaimer
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

Description

The DP83TC816-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded, shielded single twisted-pair cables with xMII interface flexibility.

DP83TC816-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping and fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB and other audio applications.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
DP83TC816-Q1 RHA (VQFN, 36) 6.00mm × 6.00mm
For more information, see Section 7.
The package size (length × width) is a nominal value and includes pins, where applicable.
DP83TC816-Q1 Simplified
                        SchematicsSimplified Schematics