SNLU131A February   2013  – June 2024

 

  1.   1
  2.   Trademarks
  3. 1 DS90UH928QEVM Introduction
    1. 1.1 DS90UH928QEVM Kit Contents
    2. 1.2 System Requirements
    3. 1.3 DS90UH928QEVM Overview
    4. 1.4 Typical Application
  4. 2Quick Start Guide
    1. 2.1 Board Setup
  5. 3Evaluation Hardware Overview
    1. 3.1  Board Overview
    2. 3.2  Power
    3. 3.3  FPD-Link Video Data Output
    4. 3.4  FPD-Link III Interface
    5. 3.5  CML Loop-thru Monitor Interface
    6. 3.6  Controller
    7. 3.7  I2C and Device Addressing
    8. 3.8  I2S and GPIO Interface
    9. 3.9  Device Address, Reset and Mode Selection Inputs
      1. 3.9.1 Output State Select (S1)
      2. 3.9.2 Mode Selection Inputs (S2)
      3. 3.9.3 I2C Address Select (IDx)
      4. 3.9.4 MODE_SEL (S5)
    10. 3.10 Indicators
    11. 3.11 Input/Output Connectors
  6. 4ALP Software
    1. 4.1 Overview
    2. 4.2 Installation
    3. 4.3 Usage
      1. 4.3.1 Information Tab
      2. 4.3.2 Pattern Generator Tab
      3. 4.3.3 Registers Tab
      4. 4.3.4 Scripting Tab
    4. 4.4 Troubleshooting
  7. 5Related Documentation
  8. 6Board Schematic
  9. 7Bill of Materials
  10. 8Board Layout and Layers
  11. 9Revision History

3.7 I2C and Device Addressing

A row of switches provided by S3 and S4 sets the IDx I2C address select. Only one I2C address can be selected at a time. Note that addresses 0x58 and 0x66 through 0x76 are available. All others are reserved.

Table 3-1 I2C Unique Address Settings for IDx
NO. ADDRESS 7'b ADDRESS 8'b
1 0x2C 0x58
2 0x33 0x66
3 0x34 0x68
4 0x35 0x6A
5 0x36 0x6C
6 0x37 0x6E
7 0x38 0x70
8 0x39 0x72
9 0x3A 0x74
10 0x3B 0x76