SNLU269 april   2023 SN75LVPE3410

 

  1.   Abstract
  2. 1Access Method
    1. 1.1 Register Programming Through SMBus
  3. 2Register Types
    1. 2.1 Channel Control Share Registers
  4. 3Example Programming Sequences
    1. 3.1 Single Channel Write Selection
    2. 3.2 Broadcast Write Selection
    3. 3.3 Set CTLE Gain Level
    4. 3.4 Set CTLE DC Gain Level
    5. 3.5 Set VOD Level
  5. 4Share Registers
  6. 5Channel Registers
  7. 6References

1.1 Register Programming Through SMBus

The SN75LVPE3410 internal registers can be accessed through standard SMBus protocol. The SMBus secondary address is determined at power up based on the configuration of the EQ1_ADDR1 and EQ0_ADDR0 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

The EQ1_ADDR1 and EQ0_ADDR0 pins along with GAIN, VOD, EN_SMB, and RX_DET pins are 4-level input pins that are used to control the configuration of the device. These 4-level inputs use a resistor divider to help set the four valid levels as shown in Table 1-1.

Table 1-1 SN75LVPE3410 4-Level Control Pin Settings
Pin LevelPin Setting
L01 kΩ to GND
L113 kΩ to GND
L2Float
L359 kΩ to GND

There are 16 unique SMBus secondary addresses that can be assigned to the device by placing external resistor straps on the EQ0_ADDR0 and EQ1_ADDR1 pins as shown in Table 1-2. When multiple SN75LVPE3410 devices are on the same SMBus interface bus, each device must be configured with a unique SMBus secondary address.

Table 1-2 SN75LVPE3410 SMBus Address Map
EQ1_ADDR1 Pin LevelEQ0_ADDR0 Pin Level7-Bit Address [HEX]8-Bit Write Address [HEX]
L0L00x180x30
L0L10x190x32
L0L20x1A0x34
L0L30x1B0x36
L1L00x1C0x38
L1L10x1D0x3A
L1L20x1E0x3C
L1L30x1F0x3E
L2L00x200x40
L2L10x210x42
L2L20x220x44
L2L30x230x46
L3L00x240x48
L3L10x250x4A
L3L20x260x4C
L3L30x270x4E