SNLU302 March   2025 DS320PR810 , DS320PR822

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Map Overview
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Example Programming Sequences
    1. 5.1 Set CTLE Gain Level
    2. 5.2 Set CTLE Flat Gain Level
    3. 5.3 Set PD Control
    4. 5.4 Set SEL Input (DS320PR822)
  9. 6References

2.2 Channel Registers

The DS320PR810 features two banks of channels, Bank 0 (Channels 0-3) and Bank 1 (Channels 4-7), each featuring a separate register set and requiring a unique SMBus secondary address.

Table 2-7 RX Detect Status Register (channel register base + offset = 0x00) [reset = 0x00]
Bit Field Type Reset Description
7 rx_det_comp_p R 0x0 Rx Detect Positive Polarity Status:
0: Not detected
1: Detected - the value is latched.
6 rx_det_comp_n R 0x0 Rx Detect Negative Polarity Status:
0: Not detected
1: Detected - the value is latched.
5:0 RESERVED R 0x0 Reserved
Table 2-8 EQ Control Register (channel register base + offset = 0x01) [reset = 0x00]
Bit Field Type Reset Description
7 eq_stage1_bypass R/W 0x0 Enable EQ Stage 1 Bypass:
0: Bypass disabled
1: Bypass enabled
6 eq_stage1_3 R/W

0x0

 EQ Boost Stage 1 Control.
For details, see the DS320PR810 data sheet.
5 eq_stage1_2 R/W 0x0
4 eq_stage1_1 R/W 0x0
3 eq_stage1_0 R/W 0x0
2 eq_stage2_2 R/W 0x0 EQ Boost Stage 2 Control.
For details, see the DS320PR810 data sheet.
1 eq_stage2_1 R/W 0x0
0 eq_stage2_0 R/W 0x0
Table 2-9 Mute EQ Control Register (channel register base + offset = 0x02) [reset = 0x00]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6:4 RESERVED R 0x0 Reserved
3 mute_eq R/W 0x0 Mute EQ output
2:0 RESERVED R 0x0 Reserved
Table 2-10 EQ Gain / Flat Gain Control Register (channel register base + offset = 0x03) [reset = 0x05]
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 eq_profile_3 R/W 0x0 EQ mid-frequency boost profile
For details, see the DS320PR810 data sheet.
5 eq_profile_2 R/W 0x0
4 eq_profile_1 R/W 0x0
3 eq_profile_0 R/W 0x0
2 flat_gain_2 R/W 0x1 Flat Gain Select.
For details, see the DS320PR810 data sheet.
1 flat_gain_1 R/W 0x0
0 flat_gain_0 R/W 0x1
Table 2-11 RX Detect Control Register (channel register base + offset = 0x04) [reset = 0x0]
Bit Field Type Reset Description
7:3 RESERVED R 0x0 Reserved
2 mr_rx_det_man R/W 0x0 Manual override of rx_detect_p/n decision:
0: Rx Detect state machine is enabled
1: Rx Detect state machine is overridden – always valid Rx termination detected
1 en_rx_det_count R/W 0x0 Enable additional Rx detect polling:
0: Additional Rx Detect Polling disabled
1: Additional Rx Detect Polling enabled
0 sel_rx_det_count R/W 0x0 Select number of Valid Rx detect polls - gated by en_rx_det_count = 1.
0: 2x consecutive valid detections
1: 3x consecutive valid detections
Table 2-12 PD Override Register (channel register base + offset = 0x05) [reset = 0x7F]
Bit Field Type Reset Description
7 device_en_override R/W 0x0 Enable power down overrides through SMBus/I2C
0: Manual override disabled
1: Manual override enabled
6:0 device_en R/W 0x7F Manual power down of redriver various blocks – gated by device_en_override = 1
0x00: All blocks are disabled
0x7F: All blocks are enabled
Table 2-13 Bias Register (channel register base + offset = 0x06) [reset = 0x20]
Bit Field Type Reset Description
7:6 RESERVED R 0x0 Reserved
5 bias_current_2 R/W 0x1 Control bias current
4 bias_current_1 R/W 0x0 See MSB.
3 bias_current_0 R/W 0x0 See MSB.
2:0 RESERVED R 0x0 Reserved