SNLU302 March   2025 DS320PR810 , DS320PR822

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Map Overview
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Example Programming Sequences
    1. 5.1 Set CTLE Gain Level
    2. 5.2 Set CTLE Flat Gain Level
    3. 5.3 Set PD Control
    4. 5.4 Set SEL Input (DS320PR822)
  9. 6References

5.2 Set CTLE Flat Gain Level

The CTLE Flat Gain (DC Gain) value can be set individually for each channel or broadcast to all channels. Table 5-5 shows an example sequence to set the Flat Gain (DC Gain) on Bank 0 and Bank 1 channels to 0dB or -4dB.

Table 5-3 Sequence to Broadcast Flat Gain Level to All Channels
Step Register Set Operation Register Address
[HEX]		 Register Value
[HEX]		 Write Mask
[HEX]		 Comment
1 Bank 0: Channels 0-3 Write 0x83 0x05 0x07 Set Flat Gain on Bank 0 channels to: 0dB (Default).
0x01 0x07 Set Flat Gain on Bank 0 channels to: -4dB.
2 Bank 1: Channels 4-7 Write 0x83 0x05 0x07 Set Flat Gain on Bank 1 channels to: 0dB (Default).
0x01 0x07 Set Flat Gain on Bank 1 channels to: -4dB.
Assuming 0x18 and 0x19 are the SMBus addresses for Channel Banks 0 and 1, respectively, the following is the XML batch script of the 0dB Flat Gain example sequence shown in Table 5-5.
<i2c_write addr="0x18" count="0" radix"16">83 05</i2c_write>
<i2c_write addr="0x19" count="0" radix"16">83 05</i2c_write>