SNLU335 October   2023 DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

Equalization Control Settings

Table 3-1 CTLE Index Equalization Settings
Equalization SettingTypical EQ Boost (dB)
EQ IndexSMBus/I2C Mode@ 8 GHz@ 16 GHz
EQ Control Register Eq_stage1_3:0EQ Control Register Eq_stage2_2:0EQ GAIN / Flat Gain Control Register Eq_profile_3:0EQ Control Register Eq_stage1_bypass
00001For values, see the DS320PR410 data sheetFor values, see the DS320PR410 data sheet
11001
23001
Default0000
50010
61010
72010
83030
94030
105170
116170
128170
1310170
14102150
15113150
16124150
17135150
18146150
19157150