SNLU335 October 2023 DS320PR410
The DS320PR410 features one bank of channels (Bank 0) consisting of Channels 0-3, which features one register set and requires one SMBus Address.
Channel Registers Base Address | Channel Bank 0 Access |
---|---|
0x00 | Channel 0 registers |
0x20 | Channel 1 registers |
0x40 | Channel 2 registers |
0x60 | Channel 3 registers |
0x80 | Broadcast write channel bank 0 registers, read channel 0 registers |
0xA0 | Broadcast write channel 0-1 registers, read channel 0 registers |
0xC0 | Broadcast write channel 2-3 registers, read channel 2 registers |
0xE0 | Channel 0-3 share registers |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | rx_det_comp_p | R | 0x0 | Rx Detect Positive Polarity Status: 0: Not detected 1: Detected - the value is latched. |
6 | rx_det_comp_n | R | 0x0 | Rx Detect Negative Polarity Status: 0: Not detected 1: Detected - the value is latched. |
5:0 | RESERVED | R | 0x0 | Reserved |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | eq_stage1_bypass | R/W | 0x0 | Enable EQ Stage 1 Bypass: 0: Bypass disabled 1: Bypass enabled |
6 | eq_stage1_3 | R/W | 0x0 | EQ Boost Stage 1 Control. For details, see the DS320PR410 data sheet. |
5 | eq_stage1_2 | R/W | 0x0 | |
4 | eq_stage1_1 | R/W | 0x0 | |
3 | eq_stage1_0 | R/W | 0x0 | |
2 | eq_stage2_2 | R/W | 0x0 | EQ Boost Stage 2 Control. For details, see the DS320PR410 data sheet. |
1 | eq_stage2_1 | R/W | 0x0 | |
0 | eq_stage2_0 | R/W | 0x0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6:4 | RESERVED | R/W | 0x0 | Reserved |
3 | mute_eq | R/W | 0x0 | Mute EQ output |
2:0 | RESERVED | R | 0x0 | Reserved |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | eq_profile_3 | R/W | 0x0 | EQ mid-frequency boost profile For details, see the DS320PR410 data sheet. |
5 | eq_profile_2 | R/W | 0x0 | |
4 | eq_profile_1 | R/W | 0x0 | |
3 | eq_profile_0 | R/W | 0x0 | |
2 | flat_gain_2 | R/W | 0x1 | Flat Gain Select. For details, see the DS320PR410 data sheet. |
1 | flat_gain_1 | R/W | 0x0 | |
0 | flat_gain_0 | R/W | 0x1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | RESERVED | R | 0x0 | Reserved |
2 | mr_rx_det_man | R/W | 0x0 | Manual override of rx_detect_p/n decision: 0: Rx Detect state machine is enabled 1: Rx Detect state machine is overridden – always valid Rx termination detected |
1 | en_rx_det_count | R/W | 0x0 | Enable additional RX detect polling: 0: Additional Rx Detect Polling disabled 1: Additional Rx Detect Polling enabled |
0 | sel_rx_det_count | R/W | 0x0 | Select number of Valid Rx detect polls - gated by en_rx_det_count = 1. 0: 2x consecutive valid detections 1: 3x consecutive valid detections |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | device_en_override | R/W | 0x0 | Enable power down overrides through SMBus/I2C 0: Manual override disabled 1: Manual override enabled |
6:0 | device_en | R/W | 0x3F | Manual power down of redriver various blocks – gated by device_en_override = 1 0x00: All blocks are disabled 0x3F: All blocks are enabled |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved |
5 | bias_current_2 | R/W | 0x1 | Control bias current |
4 | bias_current_1 | R/W | 0x0 | See MSB. |
3 | bias_current_0 | R/W | 0x0 | See MSB. |
2:0 | RESERVED | R | 0x0 | Reserved |