SNLU335 October 2023 DS320PR410
The DS320PR410 internal registers can be accessed through the standard SMBus protocol. The SMBus secondary address is determined at power up based on the configuration of the EQ1 / ADDR1 and EQ0 / ADDR0 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.
The EQ1 / ADDR1 and EQ0 / ADDR0 pins along with GAIN, MODE, and RX_DET pins are 5-level input pins that are used to control the configuration of the device. These 5-level inputs use a resistor divider to help set the four valid levels as provided in Table 1-1.
Pin Level | Pin Setting |
---|---|
L0 | 1 kΩ to GND |
L1 | 8.25 kΩ to GND |
L2 | 24.9 kΩ to GND |
L3 | 75 kΩ to GND |
L3 | F (Float) |
There are 16 unique SMBus secondary addresses that can be assigned to the device by placing external resistor straps on the EQ0 / ADDR0 and EQ1 / ADDR1 pins as provided in Table 1-2. When multiple DS320PR410 devices are on the same SMBus interface bus, each device must be configured with a unique SMBus secondary address.
EQ1 / ADDR1 Pin Level | EQ0 / ADDR0 Pin Level | 7-Bit Address [HEX] |
---|---|---|
L0 | L0 | 0x18 |
L0 | L1 | 0x1A |
L0 | L2 | 0x1C |
L0 | L3 | 0x1E |
L0 | L4 | Reserved |
L1 | L0 | 0x20 |
L1 | L1 | 0x22 |
L1 | L2 | 0x24 |
L1 | L3 | 0x26 |
L1 | L4 | Reserved |
L2 | L0 | 0x28 |
L2 | L1 | 0x2A |
L2 | L2 | 0x2C |
L2 | L3 | 0x2E |
L2 | L4 | Reserved |
L3 | L0 | 0x30 |
L3 | L1 | 0x32 |
L3 | L2 | 0x34 |
L3 | L3 | 0x36 |
L3 | L4 | Reserved |