SNLU354 November   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Getting Started
    2. 2.2 EVM Configuration
      1. 2.2.1 Power Modes
        1. 2.2.1.1 Self-Powered Configuration
        2. 2.2.1.2 Bus-Powered Configuration
        3. 2.2.1.3 External Power
      2. 2.2.2 Functional Modes
        1. 2.2.2.1 I2C-Enabled Repeater Mode
        2. 2.2.2.2 GPIO Repeater Mode
        3. 2.2.2.3 UART Mode
      3. 2.2.3 I/O and Interrupts
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
    2. 4.2 Related Documentation

3.2 Board Layout

The TUSB2E221QFNEVM uses the following layout considerations:

  • USB 2.0 signals impedance controlled 90Ω differential ±5%.
  • eUSB2 signals impedance controlled 45Ω signal ended ±5%.
  • USB 2.0 and eUSB2 signal pairs routed with matched trace lengths and minimal vias.
  • All other signals to be impedance controlled 45Ω ±10% or 50Ω ±10%.

A 4-layer stack-up was used for the TUSB2E221QFNEVM.

TUSB2E221QFNEVM TUSB2E221QFNEVM PCB Top LayerFigure 3-2 TUSB2E221QFNEVM PCB Top Layer
TUSB2E221QFNEVM TUSB2E221QFNEVM PCB Layer 3 (Power Plane)Figure 3-4 TUSB2E221QFNEVM PCB Layer 3 (Power Plane)
TUSB2E221QFNEVM TUSB2E221QFNEVM PCB Layer 2 (Ground Plane)Figure 3-3 TUSB2E221QFNEVM PCB Layer 2 (Ground Plane)
TUSB2E221QFNEVM TUSB2E221QFNEVM Layer 4 (Bottom)Figure 3-5 TUSB2E221QFNEVM Layer 4 (Bottom)