SNOS491E February   2000  – March 2025 LM4051-N

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 LM4051-1.2 Electrical Characteristics
    6. 5.6 LM4051-ADJ Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 LM4051-N-1.2 V
      2. 7.4.2 LM4051-N - ADJ
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Shunt Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Adjustable Shunt Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.2 Detailed Design Procedure

To program the cathode voltage to a regulated voltage a resistive bridge must be shunted between the cathode and anode pins with the mid point tied to the reference pin. This can be seen in Figure 8-3, with R1 & R2 being the resistive bridge. The cathode/output voltage in the shunt regulator configuration can be approximated by the equation shown in Equation 7. The cathode voltage can be more accurately determined by taking in to account the cathode current shown in equation Equation 8.

Equation 7. LM4051-N
Equation 8. LM4051-N

For this equation to be valid, LM4051-ADJ must be fully biased so there is enough open loop gain to mitigate any gain error. This can be done be meeting the IRMIN denoted in Section 5.6. When the output voltage, VZ, is set below 2.5V on adjustable versions of LM4051-N, the device can experience increased reference voltage change with output voltage change (ΔVREF/ΔVO) when compared to output voltages set equal to or above 2.5V