SNOS725E May   1999  – March 2025 LMC6462 , LMC6464

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for LMC6462
    5. 5.5 Thermal Information for LMC6464
    6. 5.6 Electrical Characteristics for VS = ±2.25V or VS = 5V
    7. 5.7 Electrical Characteristics for VS = ±1.5V or VS = 3V
  7. 6 Typical Characteristics
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Common-Mode Voltage Range
      2. 7.1.2 Rail-to-Rail Output
      3. 7.1.3 Capacitive Load Tolerance
      4. 7.1.4 Compensating for Input Capacitance
      5. 7.1.5 Offset Voltage Adjustment
      6. 7.1.6 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 Transducer Interface Circuits
      2. 7.2.2 LMC646x as a Comparator
      3. 7.2.3 Half-Wave and Full-Wave Rectifiers
      4. 7.2.4 Precision Current Source
      5. 7.2.5 Oscillators
      6. 7.2.6 Low Frequency Null
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 PCB Layout for High-Impedance Work
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics for VS = ±2.25V or VS = 5V

at TA = TJ = 25°C, V+ = 5V, V– = 0V, VCM = VOUT = V+ / 2, and RL > 1MΩ connected to V+ / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage  LMC646xA   ±0.25 ±0.50 mV
TJ = –40°C to +85°C ±1.2
LMC646xB  ±0.25 ±3
TJ = –40°C to +85°C ±3.7
dVOS/dT Input offset voltage drift TJ = –40°C to +85°C 1 µV/°C
PSRR Power-supply rejection ratio Positive
5V ≤ V+ ≤ 15V
 		 LMC646xA 70 85 dB
LMC646xA,
TJ = –40°C to +85°C		 67
LMC646xB 65 85
LMC646xB,
TJ = –40°C to +85°C		 62
Negative
V+ = 0V, –15V ≤ V– ≤ –5V
 		 LMC646xA 70 85
LMC646xA,
TJ = –40°C to +85°C		 67
LMC646xB 65 85
LMC646xB,
TJ = –40°C to +85°C		 62
INPUT BIAS CURRENT
IB Input bias current(1) ±0.15 pA
TJ = –40°C to +85°C ±10
IOS Input offset current(1) ±0.075 pA
TJ = –40°C to +85°C ±5
NOISE
en Input voltage noise density f = 1kHz, VCM = 1V 80 nV/√Hz
in Input current noise density f = 1kHz 30 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage To positive rail
V+ = 5V, CMRR ≥ 50dB		 5.25 5.30 V
TJ = –40°C to +85°C 5.00
To negative rail
V+ = 5V, CMRR ≥ 50dB		 –0.20 –0.10
TJ = –40°C to +85°C 0.00
To positive rail
V+ = 5V, CMRR ≥ 50dB		 15.25 15.30
TJ = –40°C to +85°C 15.00
To negative rail
V+ = 5V, CMRR ≥ 50dB		 –0.20 –0.15
TJ = –40°C to +85°C 0.00
CMRR Common-mode rejection ratio V+ = 15V
0V ≤ VCM ≤ 15V		 LMC646xA 70 85 dB
LMC646xA,
TJ = –40°C to +85°C		 67
LMC646xB 65 85
LMC646xB,
TJ = –40°C to +85°C		 62
V+ = 5V
0V ≤ VCM ≤ 5V		 LMC646xA 70 85
LMC646xA,
TJ = –40°C to +85°C		 67
LMC646xB 65 85
LMC646xB,
TJ = –40°C to +85°C		 62
INPUT IMPEDANCE
RIN Input resistance > 10 TΩ
CIN Common-mode input capacitance 3 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain  Sourcing, V+ = 15V,
7.5V < VO < 11.5V, VCM = 7.5V,		 RL = 100kΩ to 7.5V 3000 V/mV
RL = 25kΩ to 7.5V 2500
Sinking, V+ = 15V,
3.5V < VO < 7.5V, VCM = 7.5V,		 RL = 100kΩ to 7.5V 400
RL = 25kΩ to 7.5V 200
FREQUENCY RESPONSE
GBW Gain bandwidth product 50 kHz
SR Slew rate(2) V+ = 15V, 10V step, G = 1 15 28 V/ms
TJ = –40°C to +85°C 8
Gm Gain margin 15 dB
Crosstalk  Dual and quad channel, V+ = 15V, RL = 100kΩ to 7.5V, f = 1kHz, VOUT = 12VPP 130 dB
OUTPUT
VO Voltage output swing Positive rail
V+ = 5V, RL = 100kΩ to V+ / 2		 LMC646xA 4.990 4.995 V
LMC646xA,
TJ = –40°C to +85°C		 4.980
LMC646xB 4.950 4.995
LMC646xB,
TJ = –40°C to +85°C		 4.925
Negative rail
V+ = 5V, RL = 100kΩ to V+ / 2		 LMC646xA 0.005 0.010
LMC646xA,
TJ = –40°C to +85°C		 0.020
LMC646xB 0.005 0.050
LMC646xB,
TJ = –40°C to +85°C		 0.075
Positive rail
V+ = 5V, RL = 25kΩ to V+ / 2		 LMC646xA 4.975 4.990
LMC646xA,
TJ = –40°C to +85°C		 4.965
LMC646xB 4.950 4.990
LMC646xB,
TJ = –40°C to +85°C		 4.850
Negative rail
V+ = 5V, RL = 25kΩ to V+ / 2		 LMC646xA 0.01 0.02
LMC646xA,
TJ = –40°C to +85°C		 0.035
LMC646xB 0.01 0.050
LMC646xB,
TJ = –40°C to +85°C		 0.150
Positive rail
V+ = 15V, RL = 100kΩ to V+ / 2		 LMC646xA 14.975 14.990
LMC646xA,
TJ = –40°C to +85°C		 14.965
LMC646xB 14.950 14.990
LMC646xB,
TJ = –40°C to +85°C		 14.925
Negative rail
V+ = 15V, RL = 100kΩ to V+ / 2		 LMC646xA 0.01 0.025
LMC646xA,
TJ = –40°C to +85°C		 0.035
LMC646xB 0.01 0.050
LMC646xB,
TJ = –40°C to +85°C		 0.075
Positive rail
V+ = 15V, RL = 25kΩ to V+ / 2		 LMC646xA 14.900 14.965
LMC646xA,
TJ = –40°C to +85°C		 14.850
LMC646xB 14.850 14.965
LMC646xB,
TJ = –40°C to +85°C		 14.800
Negative rail
V+ = 15V, RL = 25kΩ to V+ / 2		 LMC646xA 0.025 0.050
LMC646xA,
TJ = –40°C to +85°C		 0.150
LMC646xB 0.025 0.100
LMC646xB,
TJ = –40°C to +85°C		 0.200
ISC Short-circuit current Sourcing
VOUT = 0V		 19 27 mA
TJ = –40°C to +85°C 15
Sinking
VOUT = 5V		 22 27
TJ = –40°C to +85°C 17
Sourcing
V+ = 15V, VOUT = 0V		 24 38
TJ = –40°C to +85°C 17
Sinking
V+ = 15V, VOUT = 12V(3)		 28 38
TJ = –40°C to +85°C  22
POWER SUPPLY
IQ Quiescent current VOUT = V+ / 2 LMC6462 40 55 µA
LMC6462, 
TJ = –40°C to +85°C		 70
LMC6464 80 110
LMC6464, 
TJ = –40°C to +85°C		 140
V+ = 15V, VOUT = V+ / 2 LMC6462 50 60
LMC6462, 
TJ = –40°C to +85°C		 70
LMC6464 90 120
LMC6464, 
TJ = –40°C to +85°C		 140
(1) Specified limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
(2) Number specified is the slower of either the positive or negative slew rates.
(3) Do not short circuit output to V+, when V+ is greater than 13V or reliability is adversely affected.