SNOSDH5 November   2024 LMG2640

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Current-Sense Emulation
      3. 7.3.3  Bootstrap Diode Function
      4. 7.3.4  Input Control Pins (EN, INL, INH)
      5. 7.3.5  INL - INH Interlock
      6. 7.3.6  AUX Supply Pin
        1. 7.3.6.1 AUX Power-On Reset
        2. 7.3.6.2 AUX Under-Voltage Lockout (UVLO)
      7. 7.3.7  BST Supply Pin
        1. 7.3.7.1 BST Power-On Reset
        2. 7.3.7.2 BST Under-Voltage Lockout (UVLO)
      8. 7.3.8  Over-Current Protection
      9. 7.3.9  Over-Temperature Protection
      10. 7.3.10 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
RDS(on)(ls) Drain-source (SW to SL) on resistance VINL = 5V, ID(ls) = 4.8A, TJ = 25°C 105 mΩ
VINL = 5V, ID(ls) = 4.8A, TJ = 125°C 200
IDSS(ls) Drain (SW to SL) leakage current VDS(hs) = 0V, VDS(ls) = 650V, TJ = 25°C 3.1 µA
VDS(hs) = 0V, VDS(ls) = 650V, TJ = 125°C 15.4
QOSS(ls) Output (SW to SL) charge VDS(hs) = 0V, VDS(ls) = 400V 33.6 nC
COSS(ls) Output (SW to SL) capacitance 51.0 pF
EOSS(ls) Output (SW to SL) capacitance stored energy 4.64 µJ
COSS,er(ls) Energy related effective output (SW to SL) capacitance 58.0 pF
COSS,tr(ls) Time related effective output (SW to SL) capacitance VDS(hs) = 0V, VDS(ls) = 0V to 400V 84.0 pF
QRR(ls) Reverse recovery charge 0 nC
HIGH-SIDE GAN POWER FET
RDS(on)(hs) Drain-source (DH to SW) on resistance VINH = 5V, ID(hs) = 4.8A, TJ = 25°C 105 mΩ
VINH = 5V, ID(hs) = 4.8A, TJ = 125°C 200
IDSS(hs) Drain (DH to SW) leakage current VDS(ls) = 0V, VDS(hs) = 650V, TJ = 25°C 3.1 µA
VDS(ls) = 0V, VDS(hs) = 650V, TJ = 125°C 15.4
QOSS(hs) Output (DH to SW) charge VDS(ls) = 0V, VDS(hs) = 400V 33.6 nC
COSS(hs) Output (DH to SW) capacitance 51.0 pF
EOSS(hs) Output (DH to SW) capacitance stored energy 4.64 µJ
COSS,er(hs) Energy related effective output (DH to SW) capacitance 58.0 pF
COSS,tr(hs) Time related effective output (DH to SW) capacitance VDS(ls) = 0V, VDS(hs) = 0V to 400V 84.0 pF
QRR(hs) Reverse recovery charge 0 nC
LOW-SIDE OVERCURRENT PROTECTION
IT(OC)(ls) Overcurrent fault – threshold current 8.2 9.1 10 A
HIGH-SIDE OVERCURRENT PROTECTION
IT(OC)(hs) Overcurrent fault – threshold current 8.2 9.1 10 A
BOOTSTRAP RECTIFIER
RDS(on) AUX to BST on resistance VINL = 5V, VAUX_BST = 1V, TJ = 25°C 8 Ω
VINL = 5V, VAUX_BST = 1V, TJ = 125°C 14
AUX to BST current limit VINL = 5V, VAUX_BST = 7V 210 240 270 mA
BST to AUX reverse current blocking threshold VINL = 5V 15 mA
CS
Current sense gain (ICS(src) / ID(LS)) VINL = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID(ls)< IT(OC)(ls) 0.616 mA/A
Current sense input offset current VINL = 5V, 0V ≤ VCS ≤ 2V, 0A ≤ ID(ls) < IT(OC)(ls) –82 82 mA
Initial held output after overcurrent fault occurs while INL remains high VINL = 5V, 0V ≤ VCS ≤ 2V 7 mA
ICS(src)(OC)(final) Final held output after overcurrent fault occurs while INL remains high VINL = 5V, 0V ≤ VCS ≤ 2V 10 12 15.5 mA
Output clamp voltage VINL = 5V, ID(ls) = 8.1A, CS sinking 5mA from external source 2.5 V
EN, INL, INH
VIT+ Positive-going input threshold voltage 1.7 2.45 V
VIT– Negative-going input threshold voltage 0.7 1.3 V
Input threshold voltage hysteresis 1 V
Pull-down input resistance 0V ≤ VPIN ≤ 3V 200 400 600 kΩ
Pull-down input current 10V ≤ VPIN ≤ 26V; VAUX = 26V 10 µA
OVER-TEMPERATURE PROTECTION
Temperature fault – postive-going threshold temperature 150 °C
Temperature fault – negative-going threshold temperature 130 °C
Temperature fault – threshold temperature hysteresis 20 °C
FLT
Low-level output voltage FLT sinking 1mA while asserted 200 mV
Off-state sink current VFLT = VAUX while de-asserted 1 µA
AUX
VAUX,T+(UVLO) UVLO – positive-going threshold voltage 8.9 9.3 9.7 V
UVLO – negative-going threshold voltage 8.6 9.0 9.4 V
UVLO – threshold voltage hysteresis 250 mV
Standby quiescent current VEN = 0V 50 80 µA
Quiescent current 250 370 µA
VINL = 5V, ID(ls) = 0A 1250 µA
Operating current VINL = 0V or 5V, VDS(ls) = 0V, ID(ls) = 0A, fINL = 500kHz 3.5 mA
BST
VBST_SW,T+(UVLO) VBST_SW UVLO for FET to turn on – positive-going threshold voltage 6.7 7 7.3 V
VBST_SW UVLO for FET to stay on– negative-going threshold voltage 4.8 5.1 5.4 V
Quiescent current 65 100 µA
VINH = 5V 350
Operating current VINH = 0V or 5V, VDS(hs) = 0V; fINH = 500kHz 2.1 mA