SNOSDK7A October   2025  – December 2025 TLV3901

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Latching/Adjustable Hysteresis
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 CML Output
      3. 6.4.3 Latch Functionality
      4. 6.4.4 Adjustable Hysteresis
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Application Overview
    2. 7.2 Typical Application
      1. 7.2.1 Optical Receiver
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Performance Plots
      2. 7.2.2 External Trigger Function for Oscilloscopes
      3. 7.2.3 Logic Clock Source to CML Transceiver
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RTE Package
16-Pad WQFN With Exposed Thermal Pad
Top View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMETLV3901
VTP1-Termination Resistor Return Pin for VP
VP2INoninverting Analog Input
VN3IInverting Analog Input
VTN4-Termination Resistor Return Pin For VN Input
VCCI5, 16-Positive Supply Voltage for Input Stage
LE6ILatch Enable Pin, Inverting Side
LE7ILatch Enable Input Pin
VCCO8-Termination Return Pin LE/LE Input Pins
VCCO9, 12-Positive Supply Voltage for CML Output Stage
Q10OInverting Output
Q11ONoninverting Output

VEE

13, 15-Negative power supply (If using single supply, connect to GND)
HYS14IHysteresis Control Pin
Thermal PAD - - Connect directly to VEE
(1) I = Input; O = Output